drashna/ryujinx
1
0
Fork 0
Code Activity Actions

Implement Ssubw_V and Usubw_V instructions. (#287)

Browse source 
* Update AOpCodeTable.cs

* Update AInstEmitSimdHelper.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdMove.cs

* Update AInstEmitSimdCmp.cs

* Update Instructions.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs
This commit is contained in:
LDj3SNuD 2018-07-19 02:06:28 +02:00 • committed by gdkchan
parent 120fe6b74a
commit fa5545aab8
8 changed files with 620 additions and 35 deletions
Download patch file Download diff file Expand all files Collapse all files

10
ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
View file

@ -1072,6 +1072,11 @@ namespace ChocolArm64.Instruction
EmitVectorSaturatingNarrowOpSxZx(Context, () => { });
}
public static void Ssubw_V(AILEmitterCtx Context)
{
EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Sub));
}
public static void Sub_S(AILEmitterCtx Context)
{
EmitScalarBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));
@ -1225,5 +1230,10 @@ namespace ChocolArm64.Instruction
{
EmitVectorSaturatingNarrowOpZxZx(Context, () => { });
}
public static void Usubw_V(AILEmitterCtx Context)
{
EmitVectorWidenRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));
}
}
}