Add intrinsics support (#121)
* Initial intrinsics support * Update tests to work with the new Vector128 type and intrinsics * Drop SSE4.1 requirement * Fix copy-paste mistake
This commit is contained in:
gdkchan
GitHub
parent
8e306b3ac1
commit
f9f111bc85
36 changed files with 1658 additions and 1111 deletions
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@ -1,6 +1,10 @@
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using ChocolArm64.State;
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using NUnit.Framework;
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using System.Runtime.Intrinsics;
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using System.Runtime.Intrinsics.X86;
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namespace Ryujinx.Tests.Cpu
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{
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public class CpuTestSimdArithmetic : CpuTest
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@ -35,13 +39,13 @@ namespace Ryujinx.Tests.Cpu
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[TestCase(0x4EE28420u, 0x0102030405060708ul, 0xAAAAAAAAAAAAAAAAul, 0x0807060504030201ul, 0x2222222222222222ul, 0x0909090909090909ul, 0xCCCCCCCCCCCCCCCCul)]
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public void Add_V(uint Opcode, ulong A0, ulong A1, ulong B0, ulong B1, ulong Result0, ulong Result1)
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{
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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AVec V2 = new AVec { X0 = B0, X1 = B1 };
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Vector128<float> V1 = MakeVectorE0E1(A0, A1);
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Vector128<float> V2 = MakeVectorE0E1(B0, B1);
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
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Assert.Multiple(() =>
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{
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Assert.AreEqual(Result0, ThreadState.V0.X0);
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Assert.AreEqual(Result1, ThreadState.V0.X1);
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Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
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Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
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});
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}
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@ -61,13 +65,13 @@ namespace Ryujinx.Tests.Cpu
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public void Fmax_V(uint A, uint B, uint C, uint D, uint Result0, uint Result1)
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{
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uint Opcode = 0x4E22F420;
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AVec V1 = new AVec { X0 = A, X1 = B };
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AVec V2 = new AVec { X0 = C, X1 = D };
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Vector128<float> V1 = MakeVectorE0E1(A, B);
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Vector128<float> V2 = MakeVectorE0E1(C, D);
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
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Assert.Multiple(() =>
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{
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Assert.AreEqual(Result0, ThreadState.V0.X0);
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Assert.AreEqual(Result1, ThreadState.V0.X1);
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Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
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Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
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});
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}
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@ -87,63 +91,68 @@ namespace Ryujinx.Tests.Cpu
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public void Fmin_V(uint A, uint B, uint C, uint D, uint Result0, uint Result1)
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{
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uint Opcode = 0x4EA2F420;
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AVec V1 = new AVec { X0 = A, X1 = B };
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AVec V2 = new AVec { X0 = C, X1 = D };
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Vector128<float> V1 = MakeVectorE0E1(A, B);
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Vector128<float> V2 = MakeVectorE0E1(C, D);
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
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Assert.Multiple(() =>
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{
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Assert.AreEqual(Result0, ThreadState.V0.X0);
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Assert.AreEqual(Result1, ThreadState.V0.X1);
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Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
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Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
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});
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}
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[Test, Description("fmul s6, s1, v0.s[2]")]
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public void Fmul_Se([Random(10)] float A, [Random(10)] float B)
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{
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AThreadState ThreadState = SingleOpcode(0x5F809826, V1: new AVec { S0 = A }, V0: new AVec { S2 = B });
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AThreadState ThreadState = SingleOpcode(0x5F809826,
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V1: Sse.SetVector128(0, 0, 0, A),
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V0: Sse.SetVector128(0, B, 0, 0));
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Assert.That(ThreadState.V6.S0, Is.EqualTo(A * B));
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Assert.That(Sse41.Extract(ThreadState.V6, (byte)0), Is.EqualTo(A * B));
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}
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[Test, Description("frecpe v2.4s, v0.4s")]
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public void Frecpe_V([Random(100)] float A)
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{
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AThreadState ThreadState = SingleOpcode(0x4EA1D802, V0: new AVec { S0 = A, S1 = A, S2 = A, S3 = A });
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AThreadState ThreadState = SingleOpcode(0x4EA1D802, V0: Sse.SetAllVector128(A));
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Assert.That(ThreadState.V2.S0, Is.EqualTo(1 / A));
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Assert.That(ThreadState.V2.S1, Is.EqualTo(1 / A));
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Assert.That(ThreadState.V2.S2, Is.EqualTo(1 / A));
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Assert.That(ThreadState.V2.S3, Is.EqualTo(1 / A));
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Assert.That(Sse41.Extract(ThreadState.V2, (byte)0), Is.EqualTo(1 / A));
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Assert.That(Sse41.Extract(ThreadState.V2, (byte)1), Is.EqualTo(1 / A));
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Assert.That(Sse41.Extract(ThreadState.V2, (byte)2), Is.EqualTo(1 / A));
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Assert.That(Sse41.Extract(ThreadState.V2, (byte)3), Is.EqualTo(1 / A));
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}
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[Test, Description("frecpe d0, d1")]
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public void Frecpe_S([Random(100)] double A)
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{
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AThreadState ThreadState = SingleOpcode(0x5EE1D820, V1: new AVec { D0 = A });
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AThreadState ThreadState = SingleOpcode(0x5EE1D820, V1: MakeVectorE0(A));
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Assert.That(ThreadState.V0.D0, Is.EqualTo(1 / A));
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Assert.That(VectorExtractDouble(ThreadState.V0, 0), Is.EqualTo(1 / A));
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}
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[Test, Description("frecps v4.4s, v2.4s, v0.4s")]
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public void Frecps_V([Random(10)] float A, [Random(10)] float B)
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{
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AThreadState ThreadState = SingleOpcode(0x4E20FC44, V2: new AVec { S0 = A, S1 = A, S2 = A, S3 = A },
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V0: new AVec { S0 = B, S1 = B, S2 = B, S3 = B });
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AThreadState ThreadState = SingleOpcode(0x4E20FC44,
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V2: Sse.SetAllVector128(A),
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V0: Sse.SetAllVector128(B));
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Assert.That(ThreadState.V4.S0, Is.EqualTo(2 - (A * B)));
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Assert.That(ThreadState.V4.S1, Is.EqualTo(2 - (A * B)));
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Assert.That(ThreadState.V4.S2, Is.EqualTo(2 - (A * B)));
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Assert.That(ThreadState.V4.S3, Is.EqualTo(2 - (A * B)));
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Assert.That(Sse41.Extract(ThreadState.V4, (byte)0), Is.EqualTo(2 - (A * B)));
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Assert.That(Sse41.Extract(ThreadState.V4, (byte)1), Is.EqualTo(2 - (A * B)));
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Assert.That(Sse41.Extract(ThreadState.V4, (byte)2), Is.EqualTo(2 - (A * B)));
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Assert.That(Sse41.Extract(ThreadState.V4, (byte)3), Is.EqualTo(2 - (A * B)));
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}
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[Test, Description("frecps d0, d1, d2")]
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public void Frecps_S([Random(10)] double A, [Random(10)] double B)
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{
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AThreadState ThreadState = SingleOpcode(0x5E62FC20, V1: new AVec { D0 = A }, V2: new AVec { D0 = B });
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AThreadState ThreadState = SingleOpcode(0x5E62FC20,
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V1: MakeVectorE0(A),
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V2: MakeVectorE0(B));
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Assert.That(ThreadState.V0.D0, Is.EqualTo(2 - (A * B)));
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Assert.That(VectorExtractDouble(ThreadState.V0, 0), Is.EqualTo(2 - (A * B)));
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}
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[TestCase(0x3FE66666u, false, 0x40000000u)]
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[TestCase(0x3F99999Au, false, 0x3F800000u)]
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[TestCase(0x404CCCCDu, false, 0x40400000u)]
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@ -189,17 +198,17 @@ namespace Ryujinx.Tests.Cpu
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{
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FpcrTemp = 0x2000000;
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}
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AVec V1 = new AVec { X0 = A };
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(0x1E264020, V1: V1, Fpcr: FpcrTemp);
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Assert.AreEqual(Result, ThreadState.V0.X0);
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Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
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}
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[TestCase(0x6E618820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
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[TestCase(0x6E618820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
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[TestCase(0x6E618820u, 0x3FF8000000000000ul, 0x3FF8000000000000ul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
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[TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x3f80000040000000ul)]
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[TestCase(0x6E219820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)]
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[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x0000000000000000ul)]
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[TestCase(0x6E219820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)]
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[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x0000000000000000ul)]
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[TestCase(0x2E219820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x0000000000000000ul)]
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[TestCase(0x2E218820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)]
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[TestCase(0x2E218820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)]
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@ -212,12 +221,12 @@ namespace Ryujinx.Tests.Cpu
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{
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FpcrTemp = 0x2000000;
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}
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AVec V1 = new AVec { X0 = A, X1 = B };
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Vector128<float> V1 = MakeVectorE0E1(A, B);
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
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Assert.Multiple(() =>
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{
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Assert.AreEqual(Result0, ThreadState.V0.X0);
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Assert.AreEqual(Result1, ThreadState.V0.X1);
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Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
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Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
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});
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}
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@ -286,9 +295,9 @@ namespace Ryujinx.Tests.Cpu
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{
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FpcrTemp |= 1 << 25;
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}
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AVec V1 = new AVec { X0 = A };
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(0x1E27C020, V1: V1, Fpcr: FpcrTemp);
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Assert.AreEqual(Result, ThreadState.V0.X0);
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Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
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}
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[TestCase(0x6EE19820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'N', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
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@ -300,11 +309,11 @@ namespace Ryujinx.Tests.Cpu
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[TestCase(0x6EE19820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
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[TestCase(0x6EE19820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
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[TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x3f80000040000000ul)]
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[TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)]
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[TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)]
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[TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)]
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[TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)]
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[TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x0000000000000000ul)]
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[TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)]
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[TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)]
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[TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x0000000000000000ul)]
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[TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x0000000000000000ul)]
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[TestCase(0x2EA19820u, 0x0000000080000000ul, 0x0000000000000000ul, 'N', false, 0x0000000080000000ul, 0x0000000000000000ul)]
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@ -348,12 +357,12 @@ namespace Ryujinx.Tests.Cpu
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{
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FpcrTemp |= 1 << 25;
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}
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AVec V1 = new AVec { X0 = A, X1 = B };
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Vector128<float> V1 = MakeVectorE0E1(A, B);
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
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Assert.Multiple(() =>
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{
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Assert.AreEqual(Result0, ThreadState.V0.X0);
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Assert.AreEqual(Result1, ThreadState.V0.X1);
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Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
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Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
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});
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}
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@ -402,15 +411,15 @@ namespace Ryujinx.Tests.Cpu
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{
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FpcrTemp = 0x2000000;
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}
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AVec V1 = new AVec { X0 = A };
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(0x1E254020, V1: V1, Fpcr: FpcrTemp);
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Assert.AreEqual(Result, ThreadState.V0.X0);
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Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
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}
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[TestCase(0x4E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
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[TestCase(0x4E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
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[TestCase(0x4E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)]
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[TestCase(0xE219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f8000003f800000ul, 0x0000000000000000ul)]
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[TestCase(0x4E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)]
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[TestCase(0xE219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f8000003f800000ul, 0x0000000000000000ul)]
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[TestCase(0xE219820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)]
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[TestCase(0xE219820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)]
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[TestCase(0xE219820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")]
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@ -422,12 +431,12 @@ namespace Ryujinx.Tests.Cpu
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{
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FpcrTemp = 0x2000000;
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}
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AVec V1 = new AVec { X0 = A, X1 = B };
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Vector128<float> V1 = MakeVectorE0E1(A, B);
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
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Assert.Multiple(() =>
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{
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Assert.AreEqual(Result0, ThreadState.V0.X0);
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Assert.AreEqual(Result1, ThreadState.V0.X1);
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Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
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Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
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});
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}
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@ -476,17 +485,17 @@ namespace Ryujinx.Tests.Cpu
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{
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FpcrTemp = 0x2000000;
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}
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AVec V1 = new AVec { X0 = A };
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(0x1E264020, V1: V1, Fpcr: FpcrTemp);
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Assert.AreEqual(Result, ThreadState.V0.X0);
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Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
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}
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[TestCase(0x4E618820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
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[TestCase(0x4E618820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
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[TestCase(0x4E618820u, 0x3FF8000000000000ul, 0x3FF8000000000000ul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
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[TestCase(0x4E218820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x3f80000040000000ul)]
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[TestCase(0x4E218820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)]
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[TestCase(0xE218820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x0000000000000000ul)]
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[TestCase(0x4E218820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)]
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[TestCase(0xE218820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x0000000000000000ul)]
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[TestCase(0xE218820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x0000000000000000ul)]
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[TestCase(0xE218820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)]
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[TestCase(0xE218820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)]
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@ -499,12 +508,12 @@ namespace Ryujinx.Tests.Cpu
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|||
{
|
||||
FpcrTemp = 0x2000000;
|
||||
}
|
||||
AVec V1 = new AVec { X0 = A, X1 = B };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.AreEqual(Result0, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result1, ThreadState.V0.X1);
|
||||
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
|
||||
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -553,15 +562,15 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
FpcrTemp = 0x2000000;
|
||||
}
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(0x1E24C020, V1: V1, Fpcr: FpcrTemp);
|
||||
Assert.AreEqual(Result, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
|
||||
}
|
||||
|
||||
[TestCase(0x4EE18820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
|
||||
[TestCase(0x4EE18820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
|
||||
[TestCase(0x4EA18820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x4000000040000000ul, 0x4000000040000000ul)]
|
||||
[TestCase(0xEA18820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x4000000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x4EA18820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x4000000040000000ul, 0x4000000040000000ul)]
|
||||
[TestCase(0xEA18820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x4000000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0xEA18820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0xEA18820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0xEA18820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")]
|
||||
|
|
@ -573,12 +582,12 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
FpcrTemp = 0x2000000;
|
||||
}
|
||||
AVec V1 = new AVec { X0 = A, X1 = B };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.AreEqual(Result0, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result1, ThreadState.V0.X1);
|
||||
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
|
||||
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -647,9 +656,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
FpcrTemp |= 1 << 25;
|
||||
}
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(0x1E274020, V1: V1, Fpcr: FpcrTemp);
|
||||
Assert.AreEqual(Result, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
|
||||
}
|
||||
|
||||
[TestCase(0x6E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'N', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
|
||||
|
|
@ -661,11 +670,11 @@ namespace Ryujinx.Tests.Cpu
|
|||
[TestCase(0x6E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
|
||||
[TestCase(0x6E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
|
||||
[TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x3f80000040000000ul)]
|
||||
[TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)]
|
||||
[TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)]
|
||||
[TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)]
|
||||
[TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)]
|
||||
[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2E219820u, 0x0000000080000000ul, 0x0000000000000000ul, 'N', false, 0x0000000080000000ul, 0x0000000000000000ul)]
|
||||
|
|
@ -709,21 +718,21 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
FpcrTemp |= 1 << 25;
|
||||
}
|
||||
AVec V1 = new AVec { X0 = A, X1 = B };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.AreEqual(Result0, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result1, ThreadState.V0.X1);
|
||||
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
|
||||
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
|
||||
});
|
||||
}
|
||||
|
||||
[TestCase(0x41200000u, 0x3EA18000u)]
|
||||
public void Frsqrte_S(uint A, uint Result)
|
||||
{
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(0x7EA1D820, V1: V1);
|
||||
Assert.AreEqual(Result, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue