Implement a new physical memory manager and replace DeviceMemory (#856)
* Implement a new physical memory manager and replace DeviceMemory * Proper generic constraints * Fix debug build * Add memory tests * New CPU memory manager and general code cleanup * Remove host memory management from CPU project, use Ryujinx.Memory instead * Fix tests * Document exceptions on MemoryBlock * Fix leak on unix memory allocation * Proper disposal of some objects on tests * Fix JitCache not being set as initialized * GetRef without checks for 8-bits and 16-bits CAS * Add MemoryBlock destructor * Throw in separate method to improve codegen * Address PR feedback * QueryModified improvements * Fix memory write tracking not marking all pages as modified in some cases * Simplify MarkRegionAsModified * Remove XML doc for ghost param * Add back optimization to avoid useless buffer updates * Add Ryujinx.Cpu project, move MemoryManager there and remove MemoryBlockWrapper * Some nits * Do not perform address translation when size is 0 * Address PR feedback and format NativeInterface class * Remove ghost parameter description * Update Ryujinx.Cpu to .NET Core 3.1 * Address PR feedback * Fix build * Return a well defined value for GetPhysicalAddress with invalid VA, and do not return unmapped ranges as modified * Typo
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126 changed files with 2176 additions and 2092 deletions
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@ -1,6 +1,5 @@
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using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Memory;
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using ARMeilleure.Translation;
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using System;
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@ -11,6 +10,9 @@ namespace ARMeilleure.Instructions
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{
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static class InstEmitMemoryHelper
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{
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private const int PageBits = 12;
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private const int PageMask = (1 << PageBits) - 1;
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private enum Extension
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{
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Zx,
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@ -318,28 +320,32 @@ namespace ARMeilleure.Instructions
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private static Operand EmitAddressCheck(ArmEmitterContext context, Operand address, int size)
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{
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long addressCheckMask = ~(context.Memory.AddressSpaceSize - 1);
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ulong addressCheckMask = ~((1UL << context.Memory.AddressSpaceBits) - 1);
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addressCheckMask |= (1u << size) - 1;
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return context.BitwiseAnd(address, Const(address.Type, addressCheckMask));
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return context.BitwiseAnd(address, Const(address.Type, (long)addressCheckMask));
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}
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private static Operand EmitPtPointerLoad(ArmEmitterContext context, Operand address, Operand lblFallbackPath)
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private static Operand EmitPtPointerLoad(ArmEmitterContext context, Operand address, Operand lblSlowPath)
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{
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Operand pte = Const(context.Memory.PageTable.ToInt64());
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int ptLevelBits = context.Memory.AddressSpaceBits - 12; // 12 = Number of page bits.
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int ptLevelSize = 1 << ptLevelBits;
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int ptLevelMask = ptLevelSize - 1;
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int bit = MemoryManager.PageBits;
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Operand pte = Const(context.Memory.PageTablePointer.ToInt64());
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int bit = PageBits;
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do
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{
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Operand addrPart = context.ShiftRightUI(address, Const(bit));
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bit += context.Memory.PtLevelBits;
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bit += ptLevelBits;
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if (bit < context.Memory.AddressSpaceBits)
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{
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addrPart = context.BitwiseAnd(addrPart, Const(addrPart.Type, context.Memory.PtLevelMask));
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addrPart = context.BitwiseAnd(addrPart, Const(addrPart.Type, ptLevelMask));
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}
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Operand pteOffset = context.ShiftLeft(addrPart, Const(3));
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@ -355,20 +361,16 @@ namespace ARMeilleure.Instructions
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}
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while (bit < context.Memory.AddressSpaceBits);
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Operand hasFlagSet = context.BitwiseAnd(pte, Const((long)MemoryManager.PteFlagsMask));
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context.BranchIfTrue(lblSlowPath, context.ICompareLess(pte, Const(0L)));
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context.BranchIfTrue(lblFallbackPath, hasFlagSet);
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Operand pageOffset = context.BitwiseAnd(address, Const(address.Type, MemoryManager.PageMask));
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Operand pageOffset = context.BitwiseAnd(address, Const(address.Type, PageMask));
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if (pageOffset.Type == OperandType.I32)
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{
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pageOffset = context.ZeroExtend32(OperandType.I64, pageOffset);
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}
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Operand physAddr = context.Add(pte, pageOffset);
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return physAddr;
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return context.Add(pte, pageOffset);
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}
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private static void EmitReadIntFallback(ArmEmitterContext context, Operand address, int rt, int size)
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