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ARMeilleure: Hardware accelerate SHA256 (#3585)

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* ARMeilleure/HardwareCapabilities: Add Sha

* ARMeilleure/Intrinsic: Add X86Sha256Rnds2

* ARmeilleure: Hardware accelerate SHA256H/SHA256H2

* ARMeilleure/Intrinsic: Add X86Sha256Msg1, X86Sha256Msg2

* ARMeilleure/Intrinsic: Add X86Palignr

* ARMeilleure: Hardware accelerate SHA256SU0, SHA256SU1

* PTC: Bump InternalVersion
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merry 2022-08-25 11:12:13 +01:00 • committed by GitHub
parent eba682b767
commit f5235fff29
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GPG key ID: 4AEE18F83AFDEB23
12 changed files with 136 additions and 37 deletions
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8
ARMeilleure/Instructions/InstEmitSimdHash32.cs
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@ -17,7 +17,7 @@ namespace ARMeilleure.Instructions
Operand n = GetVecA32(op.Qn);
Operand m = GetVecA32(op.Qm);
Operand res = context.Call(typeof(SoftFallback).GetMethod(nameof(SoftFallback.HashLower)), d, n, m);
Operand res = InstEmitSimdHashHelper.EmitSha256h(context, d, n, m, part2: false);
context.Copy(GetVecA32(op.Qd), res);
}
@ -30,7 +30,7 @@ namespace ARMeilleure.Instructions
Operand n = GetVecA32(op.Qn);
Operand m = GetVecA32(op.Qm);
Operand res = context.Call(typeof(SoftFallback).GetMethod(nameof(SoftFallback.HashUpper)), d, n, m);
Operand res = InstEmitSimdHashHelper.EmitSha256h(context, n, d, m, part2: true);
context.Copy(GetVecA32(op.Qd), res);
}
@ -42,7 +42,7 @@ namespace ARMeilleure.Instructions
Operand d = GetVecA32(op.Qd);
Operand m = GetVecA32(op.Qm);
Operand res = context.Call(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Sha256SchedulePart1)), d, m);
Operand res = InstEmitSimdHashHelper.EmitSha256su0(context, d, m);
context.Copy(GetVecA32(op.Qd), res);
}
@ -55,7 +55,7 @@ namespace ARMeilleure.Instructions
Operand n = GetVecA32(op.Qn);
Operand m = GetVecA32(op.Qm);
Operand res = context.Call(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Sha256SchedulePart2)), d, n, m);
Operand res = InstEmitSimdHashHelper.EmitSha256su1(context, d, n, m);
context.Copy(GetVecA32(op.Qd), res);
}