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Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)

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* Add host CPU memory barriers for DMB/DSB and ordered load/store

* PPTC version bump

* Revert to old barrier order
This commit is contained in:
gdkchan 2022-01-21 12:47:34 -03:00 • committed by GitHub
parent 7e967d796c
commit f0824fde9f
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GPG key ID: 4AEE18F83AFDEB23
6 changed files with 21 additions and 5 deletions
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8
ARMeilleure/CodeGen/X86/CodeGenerator.cs
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@ -49,6 +49,7 @@ namespace ARMeilleure.CodeGen.X86
Add(Instruction.Load, GenerateLoad);
Add(Instruction.Load16, GenerateLoad16);
Add(Instruction.Load8, GenerateLoad8);
Add(Instruction.MemoryBarrier, GenerateMemoryBarrier);
Add(Instruction.Multiply, GenerateMultiply);
Add(Instruction.Multiply64HighSI, GenerateMultiply64HighSI);
Add(Instruction.Multiply64HighUI, GenerateMultiply64HighUI);
@ -538,7 +539,7 @@ namespace ARMeilleure.CodeGen.X86
context.Assembler.Lea(dest, memOp, dest.Type);
}
}
else
else
{
ValidateBinOp(dest, src1, src2);
@ -976,6 +977,11 @@ namespace ARMeilleure.CodeGen.X86
context.Assembler.Movzx8(value, address, value.Type);
}
private static void GenerateMemoryBarrier(CodeGenContext context, Operation operation)
{
context.Assembler.LockOr(MemoryOp(OperandType.I64, Register(X86Register.Rsp)), Const(0), OperandType.I32);
}
private static void GenerateMultiply(CodeGenContext context, Operation operation)
{
Operand dest = operation.Destination;