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Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)

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* Add host CPU memory barriers for DMB/DSB and ordered load/store

* PPTC version bump

* Revert to old barrier order
This commit is contained in:
gdkchan 2022-01-21 12:47:34 -03:00 • committed by GitHub
parent 7e967d796c
commit f0824fde9f
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6 changed files with 21 additions and 5 deletions
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6
ARMeilleure/CodeGen/X86/Assembler.cs
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@ -358,6 +358,12 @@ namespace ARMeilleure.CodeGen.X86
WriteInstruction(dest, source, type, X86Instruction.Lea);
}
public void LockOr(Operand dest, Operand source, OperandType type)
{
WriteByte(LockPrefix);
WriteInstruction(dest, source, type, X86Instruction.Or);
}
public void Mov(Operand dest, Operand source, OperandType type)
{
WriteInstruction(dest, source, type, X86Instruction.Mov);