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Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468)

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* Update CpuTest.cs

* Update CpuTestSimd.cs

* Superseded.

* Update AInstEmitSimdCvt.cs

* Update ASoftFloat.cs

* Nit.

* Update PackageReferences.

* Update AInstEmitSimdArithmetic.cs

* Update AVectorHelper.cs

* Update ASoftFloat.cs

* Update ASoftFallback.cs

* Update AThreadState.cs

* Create FPType.cs

* Create FPExc.cs

* Create FPCR.cs

* Create FPSR.cs

* Update ARoundMode.cs

* Update APState.cs

* Avoid an unwanted implicit cast of the operator >= to long, continuing to check for negative values. Remove a leftover.

* Nits.
This commit is contained in:
LDj3SNuD 2018-10-23 16:12:45 +02:00 • committed by gdkchan
parent 7920dc1d2f
commit e674b37710
18 changed files with 863 additions and 200 deletions
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42
Ryujinx.Tests/Cpu/CpuTest.cs
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@ -178,11 +178,30 @@ namespace Ryujinx.Tests.Cpu
return GetThreadState();
}
/// <summary>Rounding Mode control field.</summary>
public enum RMode
{
/// <summary>Round to Nearest (RN) mode.</summary>
RN,
/// <summary>Round towards Plus Infinity (RP) mode.</summary>
RP,
/// <summary>Round towards Minus Infinity (RM) mode.</summary>
RM,
/// <summary>Round towards Zero (RZ) mode.</summary>
RZ
};
/// <summary>Floating-point Control Register.</summary>
protected enum FPCR
{
/// <summary>Rounding Mode control field.</summary>
RMode = 22,
/// <summary>Flush-to-zero mode control bit.</summary>
FZ = 24,
/// <summary>Default NaN mode control bit.</summary>
DN = 25
DN = 25,
/// <summary>Alternative half-precision control bit.</summary>
AHP = 26
}
/// <summary>Floating-point Status Register.</summary>
@ -514,6 +533,27 @@ namespace Ryujinx.Tests.Cpu
return Sse41.Extract(Sse.StaticCast<float, ulong>(Vector), (byte)1);
}
protected static ushort GenNormal_H()
{
uint Rnd;
do Rnd = TestContext.CurrentContext.Random.NextUShort();
while (( Rnd & 0x7C00u) == 0u ||
(~Rnd & 0x7C00u) == 0u);
return (ushort)Rnd;
}
protected static ushort GenSubnormal_H()
{
uint Rnd;
do Rnd = TestContext.CurrentContext.Random.NextUShort();
while ((Rnd & 0x03FFu) == 0u);
return (ushort)(Rnd & 0x83FFu);
}
protected static uint GenNormal_S()
{
uint Rnd;