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Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468)

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* Update CpuTest.cs

* Update CpuTestSimd.cs

* Superseded.

* Update AInstEmitSimdCvt.cs

* Update ASoftFloat.cs

* Nit.

* Update PackageReferences.

* Update AInstEmitSimdArithmetic.cs

* Update AVectorHelper.cs

* Update ASoftFloat.cs

* Update ASoftFallback.cs

* Update AThreadState.cs

* Create FPType.cs

* Create FPExc.cs

* Create FPCR.cs

* Create FPSR.cs

* Update ARoundMode.cs

* Update APState.cs

* Avoid an unwanted implicit cast of the operator >= to long, continuing to check for negative values. Remove a leftover.

* Nits.
This commit is contained in:
LDj3SNuD 2018-10-23 16:12:45 +02:00 • committed by gdkchan
parent 7920dc1d2f
commit e674b37710
18 changed files with 863 additions and 200 deletions
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8
ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
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@ -835,8 +835,6 @@ namespace ChocolArm64.Instruction
{
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Fpcr));
if (Op.Size == 0)
{
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.RoundF));
@ -862,8 +860,6 @@ namespace ChocolArm64.Instruction
{
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Fpcr));
if (SizeF == 0)
{
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.RoundF));
@ -938,8 +934,6 @@ namespace ChocolArm64.Instruction
{
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Fpcr));
if (Op.Size == 0)
{
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.RoundF));
@ -963,8 +957,6 @@ namespace ChocolArm64.Instruction
{
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Fpcr));
if (Op.Size == 0)
{
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.RoundF));