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Add Sse Opt. for S/Umax_V, S/Umin_V, S/Uaddw_V, S/Usubw_V, Fabs_S/V, Fneg_S/V Inst.; for Fcvtl_V, Fcvtn_V Inst.; and for Fcmp_S Inst.. Add/Improve other Sse Opt.. Add Tests. (#496)

Browse source 
* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update InstEmitSimdCmp.cs

* Update SoftFloat.cs

* Update InstEmitAluHelper.cs

* Update InstEmitSimdArithmetic.cs

* Update InstEmitSimdHelper.cs

* Update VectorHelper.cs

* Update InstEmitSimdCvt.cs

* Update InstEmitSimdArithmetic.cs

* Update CpuTestSimd.cs

* Update InstEmitSimdArithmetic.cs

* Update OpCodeTable.cs

* Update InstEmitSimdArithmetic.cs

* Update InstEmitSimdCmp.cs

* Update InstEmitSimdCvt.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Create CpuTestSimdFcond.cs

* Update OpCodeTable.cs

* Update InstEmitSimdMove.cs

* Update CpuTestSimdIns.cs

* Create CpuTestSimdExt.cs

* Nit.

* Update PackageReference.
This commit is contained in:
LDj3SNuD 2018-11-18 03:41:16 +01:00 • committed by gdkchan
parent b7613dd4b8
commit e603b7afbc
16 changed files with 2049 additions and 337 deletions
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74
ChocolArm64/Instructions/SoftFloat.cs
View file

@ -789,6 +789,43 @@ namespace ChocolArm64.Instructions
return result;
}
public static int FPCompare(float value1, float value2, bool signalNaNs, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPCompare: state.Fpcr = 0x{state.Fpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out _, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out _, state);
int result;
if (type1 == FpType.SNaN || type1 == FpType.QNaN || type2 == FpType.SNaN || type2 == FpType.QNaN)
{
result = 0b0011;
if (type1 == FpType.SNaN || type2 == FpType.SNaN || signalNaNs)
{
FPProcessException(FpExc.InvalidOp, state);
}
}
else
{
if (value1 == value2)
{
result = 0b0110;
}
else if (value1 < value2)
{
result = 0b1000;
}
else
{
result = 0b0010;
}
}
return result;
}
public static float FPDiv(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPDiv: state.Fpcr = 0x{state.Fpcr:X8}");
@ -1584,6 +1621,43 @@ namespace ChocolArm64.Instructions
return result;
}
public static int FPCompare(double value1, double value2, bool signalNaNs, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPCompare: state.Fpcr = 0x{state.Fpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out _, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out _, state);
int result;
if (type1 == FpType.SNaN || type1 == FpType.QNaN || type2 == FpType.SNaN || type2 == FpType.QNaN)
{
result = 0b0011;
if (type1 == FpType.SNaN || type2 == FpType.SNaN || signalNaNs)
{
FPProcessException(FpExc.InvalidOp, state);
}
}
else
{
if (value1 == value2)
{
result = 0b0110;
}
else if (value1 < value2)
{
result = 0b1000;
}
else
{
result = 0b0010;
}
}
return result;
}
public static double FPDiv(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPDiv: state.Fpcr = 0x{state.Fpcr:X8}");