Add Sse Opt. for S/Umax_V, S/Umin_V, S/Uaddw_V, S/Usubw_V, Fabs_S/V, Fneg_S/V Inst.; for Fcvtl_V, Fcvtn_V Inst.; and for Fcmp_S Inst.. Add/Improve other Sse Opt.. Add Tests. (#496)
* Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update InstEmitSimdCmp.cs * Update SoftFloat.cs * Update InstEmitAluHelper.cs * Update InstEmitSimdArithmetic.cs * Update InstEmitSimdHelper.cs * Update VectorHelper.cs * Update InstEmitSimdCvt.cs * Update InstEmitSimdArithmetic.cs * Update CpuTestSimd.cs * Update InstEmitSimdArithmetic.cs * Update OpCodeTable.cs * Update InstEmitSimdArithmetic.cs * Update InstEmitSimdCmp.cs * Update InstEmitSimdCvt.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Create CpuTestSimdFcond.cs * Update OpCodeTable.cs * Update InstEmitSimdMove.cs * Update CpuTestSimdIns.cs * Create CpuTestSimdExt.cs * Nit. * Update PackageReference.
This commit is contained in:
LDj3SNuD
gdkchan
parent
b7613dd4b8
commit
e603b7afbc
16 changed files with 2049 additions and 337 deletions
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@ -186,18 +186,101 @@ namespace ChocolArm64.Instructions
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public static void Fabs_S(ILEmitterCtx context)
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{
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EmitScalarUnaryOpF(context, () =>
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if (Optimizations.UseSse2)
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{
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EmitUnaryMathCall(context, nameof(Math.Abs));
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});
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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if (op.Size == 0)
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{
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Type[] typesSsv = new Type[] { typeof(float) };
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Type[] typesAndNot = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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context.EmitLdc_R4(-0f);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.SetScalarVector128), typesSsv));
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context.EmitLdvec(op.Rn);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.AndNot), typesAndNot));
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context.EmitStvec(op.Rd);
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EmitVectorZero32_128(context, op.Rd);
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}
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else /* if (op.Size == 1) */
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{
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Type[] typesSsv = new Type[] { typeof(double) };
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Type[] typesAndNot = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
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context.EmitLdc_R8(-0d);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetScalarVector128), typesSsv));
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EmitLdvecWithCastToDouble(context, op.Rn);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesAndNot));
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EmitStvecWithCastFromDouble(context, op.Rd);
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else
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{
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EmitScalarUnaryOpF(context, () =>
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{
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EmitUnaryMathCall(context, nameof(Math.Abs));
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});
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}
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}
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public static void Fabs_V(ILEmitterCtx context)
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{
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EmitVectorUnaryOpF(context, () =>
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if (Optimizations.UseSse2)
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{
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EmitUnaryMathCall(context, nameof(Math.Abs));
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});
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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int sizeF = op.Size & 1;
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if (sizeF == 0)
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{
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Type[] typesSav = new Type[] { typeof(float) };
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Type[] typesAndNot = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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context.EmitLdc_R4(-0f);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.SetAllVector128), typesSav));
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context.EmitLdvec(op.Rn);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.AndNot), typesAndNot));
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context.EmitStvec(op.Rd);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else /* if (sizeF == 1) */
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{
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Type[] typesSav = new Type[] { typeof(double) };
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Type[] typesAndNot = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
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context.EmitLdc_R8(-0d);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
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EmitLdvecWithCastToDouble(context, op.Rn);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesAndNot));
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EmitStvecWithCastFromDouble(context, op.Rd);
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}
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}
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else
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{
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EmitVectorUnaryOpF(context, () =>
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{
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EmitUnaryMathCall(context, nameof(Math.Abs));
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});
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}
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}
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public static void Fadd_S(ILEmitterCtx context)
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@ -283,7 +366,7 @@ namespace ChocolArm64.Instructions
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}
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}
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public static void Fmadd_S(ILEmitterCtx context)
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public static void Fmadd_S(ILEmitterCtx context) // Fused.
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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@ -450,22 +533,118 @@ namespace ChocolArm64.Instructions
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});
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}
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public static void Fmla_V(ILEmitterCtx context)
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public static void Fmla_V(ILEmitterCtx context) // Fused.
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{
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EmitVectorTernaryOpF(context, () =>
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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context.Emit(OpCodes.Mul);
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context.Emit(OpCodes.Add);
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});
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OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
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int sizeF = op.Size & 1;
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if (sizeF == 0)
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{
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Type[] typesMulAdd = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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context.EmitLdvec(op.Rd);
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context.EmitLdvec(op.Rn);
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context.EmitLdvec(op.Rm);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Multiply), typesMulAdd));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Add), typesMulAdd));
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context.EmitStvec(op.Rd);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else /* if (sizeF == 1) */
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{
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Type[] typesMulAdd = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
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EmitLdvecWithCastToDouble(context, op.Rd);
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EmitLdvecWithCastToDouble(context, op.Rn);
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EmitLdvecWithCastToDouble(context, op.Rm);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Multiply), typesMulAdd));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), typesMulAdd));
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EmitStvecWithCastFromDouble(context, op.Rd);
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}
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}
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else
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{
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EmitVectorTernaryOpF(context, () =>
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{
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EmitSoftFloatCall(context, nameof(SoftFloat32.FPMulAdd));
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});
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}
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}
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public static void Fmla_Ve(ILEmitterCtx context)
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public static void Fmla_Ve(ILEmitterCtx context) // Fused.
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{
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EmitVectorTernaryOpByElemF(context, () =>
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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context.Emit(OpCodes.Mul);
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context.Emit(OpCodes.Add);
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});
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OpCodeSimdRegElemF64 op = (OpCodeSimdRegElemF64)context.CurrOp;
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int sizeF = op.Size & 1;
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if (sizeF == 0)
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{
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Type[] typesSfl = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>), typeof(byte) };
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Type[] typesMulAdd = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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context.EmitLdvec(op.Rd);
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context.EmitLdvec(op.Rn);
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context.EmitLdvec(op.Rm);
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context.Emit(OpCodes.Dup);
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context.EmitLdc_I4(op.Index | op.Index << 2 | op.Index << 4 | op.Index << 6);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Multiply), typesMulAdd));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Add), typesMulAdd));
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context.EmitStvec(op.Rd);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else /* if (sizeF == 1) */
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{
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Type[] typesSfl = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>), typeof(byte) };
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Type[] typesMulAdd = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
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EmitLdvecWithCastToDouble(context, op.Rd);
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EmitLdvecWithCastToDouble(context, op.Rn);
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EmitLdvecWithCastToDouble(context, op.Rm);
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context.Emit(OpCodes.Dup);
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context.EmitLdc_I4(op.Index | op.Index << 1);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Multiply), typesMulAdd));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), typesMulAdd));
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EmitStvecWithCastFromDouble(context, op.Rd);
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}
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}
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else
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{
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EmitVectorTernaryOpByElemF(context, () =>
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{
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EmitSoftFloatCall(context, nameof(SoftFloat32.FPMulAdd));
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});
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}
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}
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public static void Fmls_Se(ILEmitterCtx context)
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@ -477,25 +656,121 @@ namespace ChocolArm64.Instructions
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});
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}
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public static void Fmls_V(ILEmitterCtx context)
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public static void Fmls_V(ILEmitterCtx context) // Fused.
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{
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EmitVectorTernaryOpF(context, () =>
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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context.Emit(OpCodes.Mul);
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context.Emit(OpCodes.Sub);
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});
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OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
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int sizeF = op.Size & 1;
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if (sizeF == 0)
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{
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Type[] typesMulSub = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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context.EmitLdvec(op.Rd);
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context.EmitLdvec(op.Rn);
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context.EmitLdvec(op.Rm);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Multiply), typesMulSub));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Subtract), typesMulSub));
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context.EmitStvec(op.Rd);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else /* if (sizeF == 1) */
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{
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Type[] typesMulSub = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
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EmitLdvecWithCastToDouble(context, op.Rd);
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EmitLdvecWithCastToDouble(context, op.Rn);
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EmitLdvecWithCastToDouble(context, op.Rm);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Multiply), typesMulSub));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Subtract), typesMulSub));
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EmitStvecWithCastFromDouble(context, op.Rd);
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}
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}
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else
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{
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EmitVectorTernaryOpF(context, () =>
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{
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EmitSoftFloatCall(context, nameof(SoftFloat32.FPMulSub));
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});
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}
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}
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public static void Fmls_Ve(ILEmitterCtx context)
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public static void Fmls_Ve(ILEmitterCtx context) // Fused.
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{
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EmitVectorTernaryOpByElemF(context, () =>
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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context.Emit(OpCodes.Mul);
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context.Emit(OpCodes.Sub);
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});
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OpCodeSimdRegElemF64 op = (OpCodeSimdRegElemF64)context.CurrOp;
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int sizeF = op.Size & 1;
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if (sizeF == 0)
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{
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Type[] typesSfl = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>), typeof(byte) };
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Type[] typesMulSub = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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context.EmitLdvec(op.Rd);
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context.EmitLdvec(op.Rn);
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context.EmitLdvec(op.Rm);
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context.Emit(OpCodes.Dup);
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context.EmitLdc_I4(op.Index | op.Index << 2 | op.Index << 4 | op.Index << 6);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Multiply), typesMulSub));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Subtract), typesMulSub));
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context.EmitStvec(op.Rd);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else /* if (sizeF == 1) */
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{
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Type[] typesSfl = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>), typeof(byte) };
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Type[] typesMulSub = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
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EmitLdvecWithCastToDouble(context, op.Rd);
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EmitLdvecWithCastToDouble(context, op.Rn);
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EmitLdvecWithCastToDouble(context, op.Rm);
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context.Emit(OpCodes.Dup);
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context.EmitLdc_I4(op.Index | op.Index << 1);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Multiply), typesMulSub));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Subtract), typesMulSub));
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EmitStvecWithCastFromDouble(context, op.Rd);
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}
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}
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else
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{
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EmitVectorTernaryOpByElemF(context, () =>
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{
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EmitSoftFloatCall(context, nameof(SoftFloat32.FPMulSub));
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});
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}
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}
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public static void Fmsub_S(ILEmitterCtx context)
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public static void Fmsub_S(ILEmitterCtx context) // Fused.
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{
|
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if (Optimizations.FastFP && Optimizations.UseSse2)
|
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{
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@ -580,7 +855,59 @@ namespace ChocolArm64.Instructions
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public static void Fmul_Ve(ILEmitterCtx context)
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{
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EmitVectorBinaryOpByElemF(context, () => context.Emit(OpCodes.Mul));
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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OpCodeSimdRegElemF64 op = (OpCodeSimdRegElemF64)context.CurrOp;
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int sizeF = op.Size & 1;
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if (sizeF == 0)
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{
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Type[] typesSfl = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>), typeof(byte) };
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Type[] typesMul = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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context.EmitLdvec(op.Rn);
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context.EmitLdvec(op.Rm);
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context.Emit(OpCodes.Dup);
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context.EmitLdc_I4(op.Index | op.Index << 2 | op.Index << 4 | op.Index << 6);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Multiply), typesMul));
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context.EmitStvec(op.Rd);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else /* if (sizeF == 1) */
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{
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Type[] typesSfl = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>), typeof(byte) };
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Type[] typesMul = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
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EmitLdvecWithCastToDouble(context, op.Rn);
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EmitLdvecWithCastToDouble(context, op.Rm);
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context.Emit(OpCodes.Dup);
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context.EmitLdc_I4(op.Index | op.Index << 1);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Multiply), typesMul));
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EmitStvecWithCastFromDouble(context, op.Rd);
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}
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}
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else
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{
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EmitVectorBinaryOpByElemF(context, () =>
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{
|
||||
EmitSoftFloatCall(context, nameof(SoftFloat32.FPMul));
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
public static void Fmulx_S(ILEmitterCtx context)
|
||||
|
|
@ -617,12 +944,95 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static void Fneg_S(ILEmitterCtx context)
|
||||
{
|
||||
EmitScalarUnaryOpF(context, () => context.Emit(OpCodes.Neg));
|
||||
if (Optimizations.UseSse2)
|
||||
{
|
||||
OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
|
||||
|
||||
if (op.Size == 0)
|
||||
{
|
||||
Type[] typesSsv = new Type[] { typeof(float) };
|
||||
Type[] typesXor = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
|
||||
|
||||
context.EmitLdc_R4(-0f);
|
||||
context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.SetScalarVector128), typesSsv));
|
||||
|
||||
context.EmitLdvec(op.Rn);
|
||||
|
||||
context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Xor), typesXor));
|
||||
|
||||
context.EmitStvec(op.Rd);
|
||||
|
||||
EmitVectorZero32_128(context, op.Rd);
|
||||
}
|
||||
else /* if (op.Size == 1) */
|
||||
{
|
||||
Type[] typesSsv = new Type[] { typeof(double) };
|
||||
Type[] typesXor = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
|
||||
|
||||
context.EmitLdc_R8(-0d);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetScalarVector128), typesSsv));
|
||||
|
||||
EmitLdvecWithCastToDouble(context, op.Rn);
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Xor), typesXor));
|
||||
|
||||
EmitStvecWithCastFromDouble(context, op.Rd);
|
||||
|
||||
EmitVectorZeroUpper(context, op.Rd);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
EmitScalarUnaryOpF(context, () => context.Emit(OpCodes.Neg));
|
||||
}
|
||||
}
|
||||
|
||||
public static void Fneg_V(ILEmitterCtx context)
|
||||
{
|
||||
EmitVectorUnaryOpF(context, () => context.Emit(OpCodes.Neg));
|
||||
if (Optimizations.UseSse2)
|
||||
{
|
||||
OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
|
||||
|
||||
int sizeF = op.Size & 1;
|
||||
|
||||
if (sizeF == 0)
|
||||
{
|
||||
Type[] typesSav = new Type[] { typeof(float) };
|
||||
Type[] typesXor = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
|
||||
|
||||
context.EmitLdc_R4(-0f);
|
||||
context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.SetAllVector128), typesSav));
|
||||
|
||||
context.EmitLdvec(op.Rn);
|
||||
|
||||
context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Xor), typesXor));
|
||||
|
||||
context.EmitStvec(op.Rd);
|
||||
|
||||
if (op.RegisterSize == RegisterSize.Simd64)
|
||||
{
|
||||
EmitVectorZeroUpper(context, op.Rd);
|
||||
}
|
||||
}
|
||||
else /* if (sizeF == 1) */
|
||||
{
|
||||
Type[] typesSav = new Type[] { typeof(double) };
|
||||
Type[] typesXor = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
|
||||
|
||||
context.EmitLdc_R8(-0d);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
|
||||
|
||||
EmitLdvecWithCastToDouble(context, op.Rn);
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Xor), typesXor));
|
||||
|
||||
EmitStvecWithCastFromDouble(context, op.Rd);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
EmitVectorUnaryOpF(context, () => context.Emit(OpCodes.Neg));
|
||||
}
|
||||
}
|
||||
|
||||
public static void Fnmadd_S(ILEmitterCtx context)
|
||||
|
|
@ -689,7 +1099,7 @@ namespace ChocolArm64.Instructions
|
|||
});
|
||||
}
|
||||
|
||||
public static void Frecps_S(ILEmitterCtx context)
|
||||
public static void Frecps_S(ILEmitterCtx context) // Fused.
|
||||
{
|
||||
if (Optimizations.FastFP && Optimizations.UseSse2)
|
||||
{
|
||||
|
|
@ -743,7 +1153,7 @@ namespace ChocolArm64.Instructions
|
|||
}
|
||||
}
|
||||
|
||||
public static void Frecps_V(ILEmitterCtx context)
|
||||
public static void Frecps_V(ILEmitterCtx context) // Fused.
|
||||
{
|
||||
if (Optimizations.FastFP && Optimizations.UseSse2)
|
||||
{
|
||||
|
|
@ -986,7 +1396,7 @@ namespace ChocolArm64.Instructions
|
|||
});
|
||||
}
|
||||
|
||||
public static void Frsqrts_S(ILEmitterCtx context)
|
||||
public static void Frsqrts_S(ILEmitterCtx context) // Fused.
|
||||
{
|
||||
if (Optimizations.FastFP && Optimizations.UseSse2)
|
||||
{
|
||||
|
|
@ -1048,7 +1458,7 @@ namespace ChocolArm64.Instructions
|
|||
}
|
||||
}
|
||||
|
||||
public static void Frsqrts_V(ILEmitterCtx context)
|
||||
public static void Frsqrts_V(ILEmitterCtx context) // Fused.
|
||||
{
|
||||
if (Optimizations.FastFP && Optimizations.UseSse2)
|
||||
{
|
||||
|
|
@ -1310,7 +1720,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
|
||||
|
||||
EmitLdvecWithUnsignedCast(context, op.Rm, op.Size);
|
||||
EmitLdvecWithSignedCast(context, op.Rm, op.Size);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
|
|
@ -1334,7 +1744,38 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static void Saddw_V(ILEmitterCtx context)
|
||||
{
|
||||
EmitVectorWidenRmBinaryOpSx(context, () => context.Emit(OpCodes.Add));
|
||||
if (Optimizations.UseSse41)
|
||||
{
|
||||
OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
|
||||
|
||||
Type[] typesSrl = new Type[] { VectorIntTypesPerSizeLog2[op.Size], typeof(byte) };
|
||||
Type[] typesCvt = new Type[] { VectorIntTypesPerSizeLog2[op.Size] };
|
||||
Type[] typesAdd = new Type[] { VectorIntTypesPerSizeLog2[op.Size + 1],
|
||||
VectorIntTypesPerSizeLog2[op.Size + 1] };
|
||||
|
||||
string[] namesCvt = new string[] { nameof(Sse41.ConvertToVector128Int16),
|
||||
nameof(Sse41.ConvertToVector128Int32),
|
||||
nameof(Sse41.ConvertToVector128Int64) };
|
||||
|
||||
int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0;
|
||||
|
||||
EmitLdvecWithSignedCast(context, op.Rn, op.Size + 1);
|
||||
|
||||
EmitLdvecWithSignedCast(context, op.Rm, op.Size);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), typesAdd));
|
||||
|
||||
EmitStvecWithSignedCast(context, op.Rd, op.Size + 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
EmitVectorWidenRmBinaryOpSx(context, () => context.Emit(OpCodes.Add));
|
||||
}
|
||||
}
|
||||
|
||||
public static void Shadd_V(ILEmitterCtx context)
|
||||
|
|
@ -1439,11 +1880,34 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static void Smax_V(ILEmitterCtx context)
|
||||
{
|
||||
Type[] types = new Type[] { typeof(long), typeof(long) };
|
||||
if (Optimizations.UseSse41)
|
||||
{
|
||||
OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
|
||||
|
||||
MethodInfo mthdInfo = typeof(Math).GetMethod(nameof(Math.Max), types);
|
||||
Type[] typesMax = new Type[] { VectorIntTypesPerSizeLog2[op.Size], VectorIntTypesPerSizeLog2[op.Size] };
|
||||
|
||||
EmitVectorBinaryOpSx(context, () => context.EmitCall(mthdInfo));
|
||||
Type typeSse = op.Size == 1 ? typeof(Sse2) : typeof(Sse41);
|
||||
|
||||
EmitLdvecWithSignedCast(context, op.Rn, op.Size);
|
||||
EmitLdvecWithSignedCast(context, op.Rm, op.Size);
|
||||
|
||||
context.EmitCall(typeSse.GetMethod(nameof(Sse2.Max), typesMax));
|
||||
|
||||
EmitStvecWithSignedCast(context, op.Rd, op.Size);
|
||||
|
||||
if (op.RegisterSize == RegisterSize.Simd64)
|
||||
{
|
||||
EmitVectorZeroUpper(context, op.Rd);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
Type[] types = new Type[] { typeof(long), typeof(long) };
|
||||
|
||||
MethodInfo mthdInfo = typeof(Math).GetMethod(nameof(Math.Max), types);
|
||||
|
||||
EmitVectorBinaryOpSx(context, () => context.EmitCall(mthdInfo));
|
||||
}
|
||||
}
|
||||
|
||||
public static void Smaxp_V(ILEmitterCtx context)
|
||||
|
|
@ -1457,11 +1921,34 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static void Smin_V(ILEmitterCtx context)
|
||||
{
|
||||
Type[] types = new Type[] { typeof(long), typeof(long) };
|
||||
if (Optimizations.UseSse41)
|
||||
{
|
||||
OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
|
||||
|
||||
MethodInfo mthdInfo = typeof(Math).GetMethod(nameof(Math.Min), types);
|
||||
Type[] typesMin = new Type[] { VectorIntTypesPerSizeLog2[op.Size], VectorIntTypesPerSizeLog2[op.Size] };
|
||||
|
||||
EmitVectorBinaryOpSx(context, () => context.EmitCall(mthdInfo));
|
||||
Type typeSse = op.Size == 1 ? typeof(Sse2) : typeof(Sse41);
|
||||
|
||||
EmitLdvecWithSignedCast(context, op.Rn, op.Size);
|
||||
EmitLdvecWithSignedCast(context, op.Rm, op.Size);
|
||||
|
||||
context.EmitCall(typeSse.GetMethod(nameof(Sse2.Min), typesMin));
|
||||
|
||||
EmitStvecWithSignedCast(context, op.Rd, op.Size);
|
||||
|
||||
if (op.RegisterSize == RegisterSize.Simd64)
|
||||
{
|
||||
EmitVectorZeroUpper(context, op.Rd);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
Type[] types = new Type[] { typeof(long), typeof(long) };
|
||||
|
||||
MethodInfo mthdInfo = typeof(Math).GetMethod(nameof(Math.Min), types);
|
||||
|
||||
EmitVectorBinaryOpSx(context, () => context.EmitCall(mthdInfo));
|
||||
}
|
||||
}
|
||||
|
||||
public static void Sminp_V(ILEmitterCtx context)
|
||||
|
|
@ -1484,7 +1971,7 @@ namespace ChocolArm64.Instructions
|
|||
Type[] typesMulAdd = new Type[] { VectorIntTypesPerSizeLog2[op.Size + 1],
|
||||
VectorIntTypesPerSizeLog2[op.Size + 1] };
|
||||
|
||||
Type typeMul = op.Size == 0 ? typeof(Sse2) : typeof(Sse41);
|
||||
Type typeSse = op.Size == 0 ? typeof(Sse2) : typeof(Sse41);
|
||||
|
||||
string nameCvt = op.Size == 0
|
||||
? nameof(Sse41.ConvertToVector128Int16)
|
||||
|
|
@ -1508,7 +1995,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(nameCvt, typesCvt));
|
||||
|
||||
context.EmitCall(typeMul.GetMethod(nameof(Sse2.MultiplyLow), typesMulAdd));
|
||||
context.EmitCall(typeSse.GetMethod(nameof(Sse2.MultiplyLow), typesMulAdd));
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), typesMulAdd));
|
||||
|
||||
|
|
@ -1535,7 +2022,7 @@ namespace ChocolArm64.Instructions
|
|||
Type[] typesMulSub = new Type[] { VectorIntTypesPerSizeLog2[op.Size + 1],
|
||||
VectorIntTypesPerSizeLog2[op.Size + 1] };
|
||||
|
||||
Type typeMul = op.Size == 0 ? typeof(Sse2) : typeof(Sse41);
|
||||
Type typeSse = op.Size == 0 ? typeof(Sse2) : typeof(Sse41);
|
||||
|
||||
string nameCvt = op.Size == 0
|
||||
? nameof(Sse41.ConvertToVector128Int16)
|
||||
|
|
@ -1559,7 +2046,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(nameCvt, typesCvt));
|
||||
|
||||
context.EmitCall(typeMul.GetMethod(nameof(Sse2.MultiplyLow), typesMulSub));
|
||||
context.EmitCall(typeSse.GetMethod(nameof(Sse2.MultiplyLow), typesMulSub));
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Subtract), typesMulSub));
|
||||
|
||||
|
|
@ -1735,7 +2222,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
|
||||
|
||||
EmitLdvecWithUnsignedCast(context, op.Rm, op.Size);
|
||||
EmitLdvecWithSignedCast(context, op.Rm, op.Size);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
|
|
@ -1754,7 +2241,38 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static void Ssubw_V(ILEmitterCtx context)
|
||||
{
|
||||
EmitVectorWidenRmBinaryOpSx(context, () => context.Emit(OpCodes.Sub));
|
||||
if (Optimizations.UseSse41)
|
||||
{
|
||||
OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
|
||||
|
||||
Type[] typesSrl = new Type[] { VectorIntTypesPerSizeLog2[op.Size], typeof(byte) };
|
||||
Type[] typesCvt = new Type[] { VectorIntTypesPerSizeLog2[op.Size] };
|
||||
Type[] typesSub = new Type[] { VectorIntTypesPerSizeLog2[op.Size + 1],
|
||||
VectorIntTypesPerSizeLog2[op.Size + 1] };
|
||||
|
||||
string[] namesCvt = new string[] { nameof(Sse41.ConvertToVector128Int16),
|
||||
nameof(Sse41.ConvertToVector128Int32),
|
||||
nameof(Sse41.ConvertToVector128Int64) };
|
||||
|
||||
int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0;
|
||||
|
||||
EmitLdvecWithSignedCast(context, op.Rn, op.Size + 1);
|
||||
|
||||
EmitLdvecWithSignedCast(context, op.Rm, op.Size);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Subtract), typesSub));
|
||||
|
||||
EmitStvecWithSignedCast(context, op.Rd, op.Size + 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
EmitVectorWidenRmBinaryOpSx(context, () => context.Emit(OpCodes.Sub));
|
||||
}
|
||||
}
|
||||
|
||||
public static void Sub_S(ILEmitterCtx context)
|
||||
|
|
@ -1901,7 +2419,38 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static void Uaddw_V(ILEmitterCtx context)
|
||||
{
|
||||
EmitVectorWidenRmBinaryOpZx(context, () => context.Emit(OpCodes.Add));
|
||||
if (Optimizations.UseSse41)
|
||||
{
|
||||
OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
|
||||
|
||||
Type[] typesSrl = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) };
|
||||
Type[] typesCvt = new Type[] { VectorUIntTypesPerSizeLog2[op.Size] };
|
||||
Type[] typesAdd = new Type[] { VectorUIntTypesPerSizeLog2[op.Size + 1],
|
||||
VectorUIntTypesPerSizeLog2[op.Size + 1] };
|
||||
|
||||
string[] namesCvt = new string[] { nameof(Sse41.ConvertToVector128Int16),
|
||||
nameof(Sse41.ConvertToVector128Int32),
|
||||
nameof(Sse41.ConvertToVector128Int64) };
|
||||
|
||||
int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0;
|
||||
|
||||
EmitLdvecWithUnsignedCast(context, op.Rn, op.Size + 1);
|
||||
|
||||
EmitLdvecWithUnsignedCast(context, op.Rm, op.Size);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), typesAdd));
|
||||
|
||||
EmitStvecWithUnsignedCast(context, op.Rd, op.Size + 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
EmitVectorWidenRmBinaryOpZx(context, () => context.Emit(OpCodes.Add));
|
||||
}
|
||||
}
|
||||
|
||||
public static void Uhadd_V(ILEmitterCtx context)
|
||||
|
|
@ -1992,11 +2541,34 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static void Umax_V(ILEmitterCtx context)
|
||||
{
|
||||
Type[] types = new Type[] { typeof(ulong), typeof(ulong) };
|
||||
if (Optimizations.UseSse41)
|
||||
{
|
||||
OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
|
||||
|
||||
MethodInfo mthdInfo = typeof(Math).GetMethod(nameof(Math.Max), types);
|
||||
Type[] typesMax = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], VectorUIntTypesPerSizeLog2[op.Size] };
|
||||
|
||||
EmitVectorBinaryOpZx(context, () => context.EmitCall(mthdInfo));
|
||||
Type typeSse = op.Size == 0 ? typeof(Sse2) : typeof(Sse41);
|
||||
|
||||
EmitLdvecWithUnsignedCast(context, op.Rn, op.Size);
|
||||
EmitLdvecWithUnsignedCast(context, op.Rm, op.Size);
|
||||
|
||||
context.EmitCall(typeSse.GetMethod(nameof(Sse2.Max), typesMax));
|
||||
|
||||
EmitStvecWithUnsignedCast(context, op.Rd, op.Size);
|
||||
|
||||
if (op.RegisterSize == RegisterSize.Simd64)
|
||||
{
|
||||
EmitVectorZeroUpper(context, op.Rd);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
Type[] types = new Type[] { typeof(ulong), typeof(ulong) };
|
||||
|
||||
MethodInfo mthdInfo = typeof(Math).GetMethod(nameof(Math.Max), types);
|
||||
|
||||
EmitVectorBinaryOpZx(context, () => context.EmitCall(mthdInfo));
|
||||
}
|
||||
}
|
||||
|
||||
public static void Umaxp_V(ILEmitterCtx context)
|
||||
|
|
@ -2010,11 +2582,34 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static void Umin_V(ILEmitterCtx context)
|
||||
{
|
||||
Type[] types = new Type[] { typeof(ulong), typeof(ulong) };
|
||||
if (Optimizations.UseSse41)
|
||||
{
|
||||
OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
|
||||
|
||||
MethodInfo mthdInfo = typeof(Math).GetMethod(nameof(Math.Min), types);
|
||||
Type[] typesMin = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], VectorUIntTypesPerSizeLog2[op.Size] };
|
||||
|
||||
EmitVectorBinaryOpZx(context, () => context.EmitCall(mthdInfo));
|
||||
Type typeSse = op.Size == 0 ? typeof(Sse2) : typeof(Sse41);
|
||||
|
||||
EmitLdvecWithUnsignedCast(context, op.Rn, op.Size);
|
||||
EmitLdvecWithUnsignedCast(context, op.Rm, op.Size);
|
||||
|
||||
context.EmitCall(typeSse.GetMethod(nameof(Sse2.Min), typesMin));
|
||||
|
||||
EmitStvecWithUnsignedCast(context, op.Rd, op.Size);
|
||||
|
||||
if (op.RegisterSize == RegisterSize.Simd64)
|
||||
{
|
||||
EmitVectorZeroUpper(context, op.Rd);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
Type[] types = new Type[] { typeof(ulong), typeof(ulong) };
|
||||
|
||||
MethodInfo mthdInfo = typeof(Math).GetMethod(nameof(Math.Min), types);
|
||||
|
||||
EmitVectorBinaryOpZx(context, () => context.EmitCall(mthdInfo));
|
||||
}
|
||||
}
|
||||
|
||||
public static void Uminp_V(ILEmitterCtx context)
|
||||
|
|
@ -2037,7 +2632,7 @@ namespace ChocolArm64.Instructions
|
|||
Type[] typesMulAdd = new Type[] { VectorIntTypesPerSizeLog2 [op.Size + 1],
|
||||
VectorIntTypesPerSizeLog2 [op.Size + 1] };
|
||||
|
||||
Type typeMul = op.Size == 0 ? typeof(Sse2) : typeof(Sse41);
|
||||
Type typeSse = op.Size == 0 ? typeof(Sse2) : typeof(Sse41);
|
||||
|
||||
string nameCvt = op.Size == 0
|
||||
? nameof(Sse41.ConvertToVector128Int16)
|
||||
|
|
@ -2061,7 +2656,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(nameCvt, typesCvt));
|
||||
|
||||
context.EmitCall(typeMul.GetMethod(nameof(Sse2.MultiplyLow), typesMulAdd));
|
||||
context.EmitCall(typeSse.GetMethod(nameof(Sse2.MultiplyLow), typesMulAdd));
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), typesMulAdd));
|
||||
|
||||
|
|
@ -2088,7 +2683,7 @@ namespace ChocolArm64.Instructions
|
|||
Type[] typesMulSub = new Type[] { VectorIntTypesPerSizeLog2 [op.Size + 1],
|
||||
VectorIntTypesPerSizeLog2 [op.Size + 1] };
|
||||
|
||||
Type typeMul = op.Size == 0 ? typeof(Sse2) : typeof(Sse41);
|
||||
Type typeSse = op.Size == 0 ? typeof(Sse2) : typeof(Sse41);
|
||||
|
||||
string nameCvt = op.Size == 0
|
||||
? nameof(Sse41.ConvertToVector128Int16)
|
||||
|
|
@ -2112,7 +2707,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(nameCvt, typesCvt));
|
||||
|
||||
context.EmitCall(typeMul.GetMethod(nameof(Sse2.MultiplyLow), typesMulSub));
|
||||
context.EmitCall(typeSse.GetMethod(nameof(Sse2.MultiplyLow), typesMulSub));
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Subtract), typesMulSub));
|
||||
|
||||
|
|
@ -2251,7 +2846,38 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static void Usubw_V(ILEmitterCtx context)
|
||||
{
|
||||
EmitVectorWidenRmBinaryOpZx(context, () => context.Emit(OpCodes.Sub));
|
||||
if (Optimizations.UseSse41)
|
||||
{
|
||||
OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
|
||||
|
||||
Type[] typesSrl = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) };
|
||||
Type[] typesCvt = new Type[] { VectorUIntTypesPerSizeLog2[op.Size] };
|
||||
Type[] typesSub = new Type[] { VectorUIntTypesPerSizeLog2[op.Size + 1],
|
||||
VectorUIntTypesPerSizeLog2[op.Size + 1] };
|
||||
|
||||
string[] namesCvt = new string[] { nameof(Sse41.ConvertToVector128Int16),
|
||||
nameof(Sse41.ConvertToVector128Int32),
|
||||
nameof(Sse41.ConvertToVector128Int64) };
|
||||
|
||||
int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0;
|
||||
|
||||
EmitLdvecWithUnsignedCast(context, op.Rn, op.Size + 1);
|
||||
|
||||
EmitLdvecWithUnsignedCast(context, op.Rm, op.Size);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Subtract), typesSub));
|
||||
|
||||
EmitStvecWithUnsignedCast(context, op.Rd, op.Size + 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
EmitVectorWidenRmBinaryOpZx(context, () => context.Emit(OpCodes.Sub));
|
||||
}
|
||||
}
|
||||
|
||||
private static void EmitAbs(ILEmitterCtx context)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue