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CPU: This PR fixes Fpscr, among other things. (#1433)

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* CPU: This PR fixes Fpscr, among other things.

* Add Fpscr.Qc = 1 if sat. for Vqrshrn & Vqrshrun.

* Fix Vcmp & Vcmpe opcode table.

* Revert "Fix Vcmp & Vcmpe opcode table."

This reverts commit c117d9410d693185ff5f8ee8e457ffbfb2027dd5.

* Address PR feedbacks.
This commit is contained in:
LDj3SNuD 2020-08-08 17:18:51 +02:00 • committed by GitHub
parent 8d59ad88b4
commit e36e97c64d
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GPG key ID: 4AEE18F83AFDEB23
19 changed files with 342 additions and 178 deletions
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16
Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs
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@ -44,7 +44,7 @@ namespace Ryujinx.Tests.Cpu
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
{
var data = GenerateVectorSequence(0x1000);
SetWorkingMemory(data);
SetWorkingMemory(0, data);
uint opcode = 0xf4a00000u; // VLD1.8 {D0[0]}, [R0], R0
@ -74,7 +74,7 @@ namespace Ryujinx.Tests.Cpu
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
{
var data = GenerateVectorSequence(0x1000);
SetWorkingMemory(data);
SetWorkingMemory(0, data);
uint opcode = 0xf4a00c00u; // VLD1.8 {D0[0]}, [R0], R0
@ -100,7 +100,7 @@ namespace Ryujinx.Tests.Cpu
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
{
var data = GenerateVectorSequence(0x1000);
SetWorkingMemory(data);
SetWorkingMemory(0, data);
uint opcode = 0xf4200000u; // VLD4.8 {D0, D1, D2, D3}, [R0], R0
@ -124,7 +124,7 @@ namespace Ryujinx.Tests.Cpu
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
{
var data = GenerateVectorSequence(0x1000);
SetWorkingMemory(data);
SetWorkingMemory(0, data);
(V128 vec1, V128 vec2, V128 vec3, V128 vec4) = GenerateTestVectors();
@ -155,7 +155,7 @@ namespace Ryujinx.Tests.Cpu
[Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
{
var data = GenerateVectorSequence(0x1000);
SetWorkingMemory(data);
SetWorkingMemory(0, data);
(V128 vec1, V128 vec2, V128 vec3, V128 vec4) = GenerateTestVectors();
@ -179,7 +179,7 @@ namespace Ryujinx.Tests.Cpu
[Values] bool single)
{
var data = GenerateVectorSequence(0x1000);
SetWorkingMemory(data);
SetWorkingMemory(0, data);
uint opcode = 0xec100a00u; // VST4.8 {D0, D1, D2, D3}, [R0], R0
@ -226,7 +226,7 @@ namespace Ryujinx.Tests.Cpu
[Values] bool sub)
{
var data = GenerateVectorSequence(0x1000);
SetWorkingMemory(data);
SetWorkingMemory(0, data);
uint opcode = 0xed900a00u; // VLDR.32 S0, [R0, #0]
opcode |= ((size & 3) << 8) | ((rn & 15) << 16);
@ -261,7 +261,7 @@ namespace Ryujinx.Tests.Cpu
[Values] bool sub)
{
var data = GenerateVectorSequence(0x1000);
SetWorkingMemory(data);
SetWorkingMemory(0, data);
uint opcode = 0xed800a00u; // VSTR.32 S0, [R0, #0]
opcode |= ((size & 3) << 8) | ((rn & 15) << 16);