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T32: Implement Asimd instructions (#3692)

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merry 2022-09-13 22:25:37 +01:00 • committed by GitHub
parent 66f16f4392
commit e05bf90af6
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23 changed files with 271 additions and 215 deletions
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5
ARMeilleure/Decoders/OpCode32SimdReg.cs
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@ -8,9 +8,10 @@
public int In => GetQuadwordSubindex(Vn) << (3 - Size);
public int Fn => GetQuadwordSubindex(Vn) << (1 - (Size & 1));
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode, false);
public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode, true);
public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
{
Vn = ((opCode >> 3) & 0x10) | ((opCode >> 16) & 0xf);