Initial support for double precision shader instructions. (#963)
* Implement DADD, DFMA and DMUL shader instructions * Rename FP to FP32 * Correct double immediate * Classic mistake
This commit is contained in:
gdkchan
GitHub
parent
3045c1a186
commit
dc97457bf0
19 changed files with 428 additions and 184 deletions
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@ -85,12 +85,19 @@ namespace Ryujinx.Graphics.Shader.Instructions
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context.Copy(GetNF(), context.ICompareLess(dest, Const(0)));
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}
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public static void SetFPZnFlags(EmitterContext context, Operand dest, bool setCC)
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public static void SetFPZnFlags(EmitterContext context, Operand dest, bool setCC, Instruction fpType = Instruction.FP32)
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{
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if (setCC)
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{
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context.Copy(GetZF(), context.FPCompareEqual(dest, ConstF(0)));
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context.Copy(GetNF(), context.FPCompareLess (dest, ConstF(0)));
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Operand zero = ConstF(0);
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if (fpType == Instruction.FP64)
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{
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zero = context.FP32ConvertToFP64(zero);
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}
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context.Copy(GetZF(), context.FPCompareEqual(dest, zero, fpType));
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context.Copy(GetNF(), context.FPCompareLess (dest, zero, fpType));
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}
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}
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}
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@ -21,31 +21,43 @@ namespace Ryujinx.Graphics.Shader.Instructions
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bool negateB = op.RawOpCode.Extract(45);
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bool absoluteB = op.RawOpCode.Extract(49);
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Operand srcB = context.FPAbsNeg(GetSrcB(context, srcType), absoluteB, negateB);
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Operand srcB = context.FPAbsNeg(GetSrcB(context, srcType), absoluteB, negateB, srcType.ToInstFPType());
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if (round)
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if (round && srcType == dstType)
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{
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switch (op.RoundingMode)
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{
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case RoundingMode.ToNearest:
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srcB = context.FPRound(srcB);
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srcB = context.FPRound(srcB, srcType.ToInstFPType());
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break;
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case RoundingMode.TowardsNegativeInfinity:
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srcB = context.FPFloor(srcB);
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srcB = context.FPFloor(srcB, srcType.ToInstFPType());
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break;
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case RoundingMode.TowardsPositiveInfinity:
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srcB = context.FPCeiling(srcB);
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srcB = context.FPCeiling(srcB, srcType.ToInstFPType());
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break;
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case RoundingMode.TowardsZero:
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srcB = context.FPTruncate(srcB);
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srcB = context.FPTruncate(srcB, srcType.ToInstFPType());
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break;
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}
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}
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srcB = context.FPSaturate(srcB, op.Saturate);
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// We don't need to handle conversions between FP16 <-> FP32
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// since we do FP16 operations as FP32 directly.
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// FP16 <-> FP64 conversions are invalid.
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if (srcType == FPType.FP32 && dstType == FPType.FP64)
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{
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srcB = context.FP32ConvertToFP64(srcB);
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}
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else if (srcType == FPType.FP64 && dstType == FPType.FP32)
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{
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srcB = context.FP64ConvertToFP32(srcB);
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}
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srcB = context.FPSaturate(srcB, op.Saturate, dstType.ToInstFPType());
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WriteFP(context, dstType, srcB);
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@ -229,9 +241,12 @@ namespace Ryujinx.Graphics.Shader.Instructions
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{
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context.Copy(dest, context.PackHalf2x16(srcB, ConstF(0)));
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}
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else
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else /* if (type == FPType.FP64) */
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{
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// TODO.
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Operand dest2 = GetDest2(context);
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context.Copy(dest, context.UnpackDouble2x32Low(srcB));
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context.Copy(dest2, context.UnpackDouble2x32High(srcB));
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}
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}
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}
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@ -11,53 +11,12 @@ namespace Ryujinx.Graphics.Shader.Instructions
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{
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static partial class InstEmit
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{
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public static void Fadd(EmitterContext context)
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{
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IOpCodeFArith op = (IOpCodeFArith)context.CurrOp;
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public static void Dadd(EmitterContext context) => EmitFPAdd(context, Instruction.FP64);
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public static void Dfma(EmitterContext context) => EmitFPFma(context, Instruction.FP64);
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public static void Dmul(EmitterContext context) => EmitFPMultiply(context, Instruction.FP64);
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bool absoluteA = op.AbsoluteA, absoluteB, negateA, negateB;
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if (op is OpCodeFArithImm32)
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{
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negateB = op.RawOpCode.Extract(53);
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negateA = op.RawOpCode.Extract(56);
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absoluteB = op.RawOpCode.Extract(57);
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}
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else
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{
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negateB = op.RawOpCode.Extract(45);
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negateA = op.RawOpCode.Extract(48);
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absoluteB = op.RawOpCode.Extract(49);
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}
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Operand srcA = context.FPAbsNeg(GetSrcA(context), absoluteA, negateA);
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Operand srcB = context.FPAbsNeg(GetSrcB(context), absoluteB, negateB);
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Operand dest = GetDest(context);
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context.Copy(dest, context.FPSaturate(context.FPAdd(srcA, srcB), op.Saturate));
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SetFPZnFlags(context, dest, op.SetCondCode);
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}
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public static void Ffma(EmitterContext context)
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{
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IOpCodeFArith op = (IOpCodeFArith)context.CurrOp;
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bool negateB = op.RawOpCode.Extract(48);
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bool negateC = op.RawOpCode.Extract(49);
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Operand srcA = GetSrcA(context);
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Operand srcB = context.FPNegate(GetSrcB(context), negateB);
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Operand srcC = context.FPNegate(GetSrcC(context), negateC);
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Operand dest = GetDest(context);
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context.Copy(dest, context.FPSaturate(context.FPFusedMultiplyAdd(srcA, srcB, srcC), op.Saturate));
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SetFPZnFlags(context, dest, op.SetCondCode);
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}
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public static void Fadd(EmitterContext context) => EmitFPAdd(context, Instruction.FP32);
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public static void Ffma(EmitterContext context) => EmitFPFma(context, Instruction.FP32);
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public static void Ffma32i(EmitterContext context)
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{
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@ -103,40 +62,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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SetFPZnFlags(context, dest, op.SetCondCode);
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}
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public static void Fmul(EmitterContext context)
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{
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IOpCodeFArith op = (IOpCodeFArith)context.CurrOp;
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bool isImm32 = op is OpCodeFArithImm32;
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bool negateB = !isImm32 && op.RawOpCode.Extract(48);
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Operand srcA = GetSrcA(context);
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Operand srcB = context.FPNegate(GetSrcB(context), negateB);
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switch (op.Scale)
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{
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case FPMultiplyScale.None: break;
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case FPMultiplyScale.Divide2: srcA = context.FPDivide (srcA, ConstF(2)); break;
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case FPMultiplyScale.Divide4: srcA = context.FPDivide (srcA, ConstF(4)); break;
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case FPMultiplyScale.Divide8: srcA = context.FPDivide (srcA, ConstF(8)); break;
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case FPMultiplyScale.Multiply2: srcA = context.FPMultiply(srcA, ConstF(2)); break;
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case FPMultiplyScale.Multiply4: srcA = context.FPMultiply(srcA, ConstF(4)); break;
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case FPMultiplyScale.Multiply8: srcA = context.FPMultiply(srcA, ConstF(8)); break;
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default: break; //TODO: Warning.
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}
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Operand dest = GetDest(context);
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bool saturate = isImm32 ? op.RawOpCode.Extract(55) : op.Saturate;
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context.Copy(dest, context.FPSaturate(context.FPMultiply(srcA, srcB), saturate));
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SetFPZnFlags(context, dest, op.SetCondCode);
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}
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public static void Fmul(EmitterContext context) => EmitFPMultiply(context, Instruction.FP32);
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public static void Fset(EmitterContext context)
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{
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@ -406,6 +332,107 @@ namespace Ryujinx.Graphics.Shader.Instructions
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context.Copy(GetDest(context), context.FPSaturate(res, op.Saturate));
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}
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private static void EmitFPAdd(EmitterContext context, Instruction fpType)
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{
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IOpCodeFArith op = (IOpCodeFArith)context.CurrOp;
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bool isFP64 = fpType == Instruction.FP64;
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bool absoluteA = op.AbsoluteA, absoluteB, negateA, negateB;
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if (op is OpCodeFArithImm32)
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{
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negateB = op.RawOpCode.Extract(53);
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negateA = op.RawOpCode.Extract(56);
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absoluteB = op.RawOpCode.Extract(57);
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}
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else
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{
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negateB = op.RawOpCode.Extract(45);
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negateA = op.RawOpCode.Extract(48);
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absoluteB = op.RawOpCode.Extract(49);
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}
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Operand srcA = context.FPAbsNeg(GetSrcA(context, isFP64), absoluteA, negateA, fpType);
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Operand srcB = context.FPAbsNeg(GetSrcB(context, isFP64), absoluteB, negateB, fpType);
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Operand res = context.FPSaturate(context.FPAdd(srcA, srcB, fpType), op.Saturate, fpType);
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SetDest(context, res, isFP64);
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SetFPZnFlags(context, res, op.SetCondCode, fpType);
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}
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private static void EmitFPFma(EmitterContext context, Instruction fpType)
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{
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IOpCodeFArith op = (IOpCodeFArith)context.CurrOp;
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bool isFP64 = fpType == Instruction.FP64;
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bool negateB = op.RawOpCode.Extract(48);
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bool negateC = op.RawOpCode.Extract(49);
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Operand srcA = GetSrcA(context, isFP64);
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Operand srcB = context.FPNegate(GetSrcB(context, isFP64), negateB, fpType);
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Operand srcC = context.FPNegate(GetSrcC(context, isFP64), negateC, fpType);
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Operand res = context.FPSaturate(context.FPFusedMultiplyAdd(srcA, srcB, srcC, fpType), op.Saturate, fpType);
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SetDest(context, res, isFP64);
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SetFPZnFlags(context, res, op.SetCondCode, fpType);
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}
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private static void EmitFPMultiply(EmitterContext context, Instruction fpType)
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{
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IOpCodeFArith op = (IOpCodeFArith)context.CurrOp;
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bool isFP64 = fpType == Instruction.FP64;
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bool isImm32 = op is OpCodeFArithImm32;
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bool negateB = !isImm32 && op.RawOpCode.Extract(48);
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Operand srcA = GetSrcA(context, isFP64);
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Operand srcB = context.FPNegate(GetSrcB(context, isFP64), negateB, fpType);
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if (op.Scale != FPMultiplyScale.None)
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{
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Operand scale = op.Scale switch
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{
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FPMultiplyScale.Divide2 => ConstF(0.5f),
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FPMultiplyScale.Divide4 => ConstF(0.25f),
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FPMultiplyScale.Divide8 => ConstF(0.125f),
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FPMultiplyScale.Multiply2 => ConstF(2f),
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FPMultiplyScale.Multiply4 => ConstF(4f),
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FPMultiplyScale.Multiply8 => ConstF(8f),
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_ => ConstF(1) // Invalid, behave as if it had no scale.
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};
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if (scale.AsFloat() == 1)
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{
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context.Config.PrintLog($"Invalid FP multiply scale \"{op.Scale}\".");
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}
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if (isFP64)
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{
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scale = context.FP32ConvertToFP64(scale);
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}
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srcA = context.FPMultiply(srcA, scale, fpType);
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}
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bool saturate = isImm32 ? op.RawOpCode.Extract(55) : op.Saturate;
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Operand res = context.FPSaturate(context.FPMultiply(srcA, srcB, fpType), saturate, fpType);
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SetDest(context, res, isFP64);
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SetFPZnFlags(context, res, op.SetCondCode, fpType);
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}
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private static Operand GetFPComparison(
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EmitterContext context,
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Condition cond,
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@ -447,7 +474,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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default: throw new InvalidOperationException($"Unexpected condition \"{cond}\".");
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}
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res = context.Add(inst | Instruction.FP, Local(), srcA, srcB);
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res = context.Add(inst | Instruction.FP32, Local(), srcA, srcB);
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if ((cond & Condition.Nan) != 0)
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{
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@ -483,5 +510,20 @@ namespace Ryujinx.Graphics.Shader.Instructions
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return FPAbsNeg(context, operands, false, op.NegateC);
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}
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private static void SetDest(EmitterContext context, Operand value, bool isFP64)
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{
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if (isFP64)
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{
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IOpCodeRd op = (IOpCodeRd)context.CurrOp;
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context.Copy(Register(op.Rd.Index, op.Rd.Type), context.UnpackDouble2x32Low(value));
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context.Copy(Register(op.Rd.Index | 1, op.Rd.Type), context.UnpackDouble2x32High(value));
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}
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else
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{
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context.Copy(GetDest(context), value);
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}
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}
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}
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}
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@ -34,9 +34,25 @@ namespace Ryujinx.Graphics.Shader.Instructions
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return Register(((IOpCodeRd)context.CurrOp).Rd);
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}
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public static Operand GetSrcA(EmitterContext context)
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public static Operand GetDest2(EmitterContext context)
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{
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return Register(((IOpCodeRa)context.CurrOp).Ra);
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Register rd = ((IOpCodeRd)context.CurrOp).Rd;
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return Register(rd.Index | 1, rd.Type);
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}
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public static Operand GetSrcA(EmitterContext context, bool isFP64 = false)
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{
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IOpCodeRa op = (IOpCodeRa)context.CurrOp;
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if (isFP64)
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{
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return context.PackDouble2x32(Register(op.Ra.Index, op.Ra.Type), Register(op.Ra.Index | 1, op.Ra.Type));
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}
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else
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{
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return Register(op.Ra);
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}
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}
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public static Operand GetSrcB(EmitterContext context, FPType floatType)
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@ -53,46 +69,78 @@ namespace Ryujinx.Graphics.Shader.Instructions
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}
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else if (floatType == FPType.FP64)
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{
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// TODO: Double floating-point type support.
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return GetSrcB(context, true);
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}
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context.Config.PrintLog($"Invalid floating point type: {floatType}.");
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return ConstF(0);
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throw new ArgumentException($"Invalid floating point type \"{floatType}\".");
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}
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public static Operand GetSrcB(EmitterContext context)
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public static Operand GetSrcB(EmitterContext context, bool isFP64 = false)
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{
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switch (context.CurrOp)
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if (isFP64)
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{
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case IOpCodeCbuf op:
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return Cbuf(op.Slot, op.Offset);
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switch (context.CurrOp)
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{
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case IOpCodeCbuf op:
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return context.PackDouble2x32(Cbuf(op.Slot, op.Offset), Cbuf(op.Slot, op.Offset + 1));
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case IOpCodeImm op:
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return Const(op.Immediate);
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case IOpCodeImmF op:
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return context.FP32ConvertToFP64(ConstF(op.Immediate));
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case IOpCodeImmF op:
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return ConstF(op.Immediate);
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case IOpCodeReg op:
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return context.PackDouble2x32(Register(op.Rb.Index, op.Rb.Type), Register(op.Rb.Index | 1, op.Rb.Type));
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case IOpCodeReg op:
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return Register(op.Rb);
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case IOpCodeRegCbuf op:
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return context.PackDouble2x32(Register(op.Rc.Index, op.Rc.Type), Register(op.Rc.Index | 1, op.Rc.Type));
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}
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}
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else
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{
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switch (context.CurrOp)
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{
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case IOpCodeCbuf op:
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return Cbuf(op.Slot, op.Offset);
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case IOpCodeRegCbuf op:
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return Register(op.Rc);
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case IOpCodeImm op:
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return Const(op.Immediate);
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case IOpCodeImmF op:
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return ConstF(op.Immediate);
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case IOpCodeReg op:
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return Register(op.Rb);
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case IOpCodeRegCbuf op:
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return Register(op.Rc);
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}
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}
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throw new InvalidOperationException($"Unexpected opcode type \"{context.CurrOp.GetType().Name}\".");
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}
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public static Operand GetSrcC(EmitterContext context)
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public static Operand GetSrcC(EmitterContext context, bool isFP64 = false)
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{
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switch (context.CurrOp)
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if (isFP64)
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{
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case IOpCodeRegCbuf op:
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return Cbuf(op.Slot, op.Offset);
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switch (context.CurrOp)
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{
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case IOpCodeRegCbuf op:
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return context.PackDouble2x32(Cbuf(op.Slot, op.Offset), Cbuf(op.Slot, op.Offset + 1));
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case IOpCodeRc op:
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return Register(op.Rc);
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case IOpCodeRc op:
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return context.PackDouble2x32(Register(op.Rc.Index, op.Rc.Type), Register(op.Rc.Index | 1, op.Rc.Type));
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}
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}
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else
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{
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switch (context.CurrOp)
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{
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case IOpCodeRegCbuf op:
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||||
return Cbuf(op.Slot, op.Offset);
|
||||
|
||||
case IOpCodeRc op:
|
||||
return Register(op.Rc);
|
||||
}
|
||||
}
|
||||
|
||||
throw new InvalidOperationException($"Unexpected opcode type \"{context.CurrOp.GetType().Name}\".");
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue