Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677)
* Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions * PPTC version * Fix VQADD/VQSUB * Improve MRC/MCR handling and exception messages In case data is being recompiled as code, we don't want to throw at emit stage, instead we should only throw if it actually tries to execute
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gdkchan
GitHub
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12 changed files with 651 additions and 193 deletions
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@ -12,11 +12,13 @@ namespace Ryujinx.Tests.Cpu
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#if SimdReg32
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#region "ValueSource (Opcodes)"
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private static uint[] _V_Add_Sub_Wide_I_()
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private static uint[] _V_Add_Sub_Long_Wide_I_()
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{
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return new uint[]
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{
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0xf2800000u, // VADDL.S8 Q0, D0, D0
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0xf2800100u, // VADDW.S8 Q0, Q0, D0
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0xf2800200u, // VSUBL.S8 Q0, D0, D0
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0xf2800300u // VSUBW.S8 Q0, Q0, D0
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};
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}
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@ -74,6 +76,15 @@ namespace Ryujinx.Tests.Cpu
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};
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}
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private static uint[] _Vmlal_Vmlsl_V_I_()
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{
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return new uint[]
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{
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0xf2800800u, // VMLAL.S8 Q0, D0, D0
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0xf2800a00u // VMLSL.S8 Q0, D0, D0
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};
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}
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private static uint[] _Vp_Add_Max_Min_F_()
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{
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return new uint[]
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@ -84,16 +95,30 @@ namespace Ryujinx.Tests.Cpu
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};
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}
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// VPADD does not have an unsigned flag, so we check the opcode before setting it.
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private static uint VpaddI8 = 0xf2000b10u; // VPADD.I8 D0, D0, D0
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private static uint[] _Vp_Add_Max_Min_I_()
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private static uint[] _Vp_Add_I_()
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{
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return new uint[]
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{
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VpaddI8,
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0xf2000a00u, // VPMAX.S8 D0, D0, D0
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0xf2000a10u // VPMIN.S8 D0, D0, D0
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0xf2000b10u // VPADD.I8 D0, D0, D0
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};
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}
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private static uint[] _V_Pmax_Pmin_Rhadd_I_()
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{
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return new uint[]
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{
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0xf2000a00u, // VPMAX .S8 D0, D0, D0
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0xf2000a10u, // VPMIN .S8 D0, D0, D0
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0xf2000100u, // VRHADD.S8 D0, D0, D0
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};
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}
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private static uint[] _Vq_Add_Sub_I_()
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{
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return new uint[]
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{
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0xf2000050u, // VQADD.S8 Q0, Q0, Q0
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0xf2000250u // VQSUB.S8 Q0, Q0, Q0
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};
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}
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#endregion
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@ -350,7 +375,7 @@ namespace Ryujinx.Tests.Cpu
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[Explicit]
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[Test, Pairwise, Description("VADD.f32 V0, V0, V0")]
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public void Vadd_f32([Values(0u)] uint rd,
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public void Vadd_F32([Values(0u)] uint rd,
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[Values(0u, 1u)] uint rn,
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[Values(0u, 2u)] uint rm,
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[ValueSource("_2S_F_")] ulong z0,
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@ -384,15 +409,15 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise]
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public void V_Add_Sub_Wide_I([ValueSource("_V_Add_Sub_Wide_I_")] uint opcode,
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[Range(0u, 5u)] uint rd,
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[Range(0u, 5u)] uint rn,
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[Range(0u, 5u)] uint rm,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong a,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong b,
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[Values(0u, 1u, 2u)] uint size, // <SU8, SU16, SU32>
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[Values] bool u) // <S, U>
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public void V_Add_Sub_Long_Wide_I([ValueSource("_V_Add_Sub_Long_Wide_I_")] uint opcode,
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[Range(0u, 5u)] uint rd,
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[Range(0u, 5u)] uint rn,
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[Range(0u, 5u)] uint rm,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong a,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong b,
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[Values(0u, 1u, 2u)] uint size, // <SU8, SU16, SU32>
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[Values] bool u) // <S, U>
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{
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if (u)
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{
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@ -566,18 +591,17 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VMLSL.<type><size> <Vd>, <Vn>, <Vm>")]
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public void Vmlsl_I([Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[Values(2u, 0u)] uint rm,
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[Values(0u, 1u, 2u)] uint size,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b,
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[Values] bool u)
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[Test, Pairwise]
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public void Vmlal_Vmlsl_I([ValueSource(nameof(_Vmlal_Vmlsl_V_I_))] uint opcode,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[Values(2u, 0u)] uint rm,
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[Values(0u, 1u, 2u)] uint size,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b,
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[Values] bool u)
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{
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uint opcode = 0xf2800a00u; // VMLSL.S8 Q0, D0, D0
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
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@ -736,17 +760,42 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise]
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public void Vp_Add_Max_Min_I([ValueSource("_Vp_Add_Max_Min_I_")] uint opcode,
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[Values(0u)] uint rd,
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[Range(0u, 5u)] uint rn,
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[Range(0u, 5u)] uint rm,
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[Values(0u, 1u, 2u)] uint size,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b,
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[Values] bool u)
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public void Vp_Add_I([ValueSource("_Vp_Add_I_")] uint opcode,
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[Values(0u)] uint rd,
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[Range(0u, 5u)] uint rn,
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[Range(0u, 5u)] uint rm,
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[Values(0u, 1u, 2u)] uint size,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b)
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{
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if (u && opcode != VpaddI8)
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
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opcode |= size << 20;
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, z);
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V128 v2 = MakeVectorE0E1(b, z);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void V_Pmax_Pmin_Rhadd_I([ValueSource("_V_Pmax_Pmin_Rhadd_I_")] uint opcode,
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[Values(0u)] uint rd,
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[Range(0u, 5u)] uint rn,
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[Range(0u, 5u)] uint rm,
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[Values(0u, 1u, 2u)] uint size,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b,
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[Values] bool u)
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{
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if (u)
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{
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opcode |= 1 << 24;
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}
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@ -765,6 +814,71 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Vq_Add_Sub_I([ValueSource("_Vq_Add_Sub_I_")] uint opcode,
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[Range(0u, 5u)] uint rd,
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[Range(0u, 5u)] uint rn,
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[Range(0u, 5u)] uint rm,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong a,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong b,
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[Values(0u, 1u, 2u)] uint size, // <SU8, SU16, SU32>
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[Values] bool u) // <S, U>
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{
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if (u)
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{
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opcode |= 1 << 24;
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}
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rd >>= 1; rd <<= 1;
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rn >>= 1; rn <<= 1;
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rm >>= 1; rm <<= 1;
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= (size & 0x3) << 20;
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V128 v0 = MakeVectorE0E1(z, ~z);
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V128 v1 = MakeVectorE0E1(a, ~a);
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V128 v2 = MakeVectorE0E1(b, ~b);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VQDMULH.<S16, S32> <Qd>, <Qn>, <Qm>")]
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public void Vqdmulh_I([Range(0u, 5u)] uint rd,
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[Range(0u, 5u)] uint rn,
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[Range(0u, 5u)] uint rm,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong z,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong a,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong b,
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[Values(1u, 2u)] uint size) // <S16, S32>
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{
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rd >>= 1; rd <<= 1;
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rn >>= 1; rn <<= 1;
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rm >>= 1; rm <<= 1;
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uint opcode = 0xf2100b40u & ~(3u << 20); // VQDMULH.S16 Q0, Q0, Q0
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= (size & 0x3) << 20;
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V128 v0 = MakeVectorE0E1(z, ~z);
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V128 v1 = MakeVectorE0E1(a, ~a);
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V128 v2 = MakeVectorE0E1(b, ~b);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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