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Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)

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* Add CRC32 A32 instructions.

* Fix CRC32 instructions.

* Add CRC intrinsic and fast path.

Loop is currently unrolled, will look into adding temp vars after tests are added.

* Begin work on Crc tests

* Fix SSE4.2 path for CRC32C, finialize tests.

* Remove unused IR path.

* Fix spacing between prefix checks.

* This should be Src.

* PTC Version

* OpCodeTable Order

* Integer check improvement. Value and Crc can be either 32 or 64 size.

* This wasn't necessary...

* If size is 3, value type must be I64.

* Fix same src+dest handling for non crc intrinsics.

* Pre-fix (ha) issue with vex encodings
This commit is contained in:
riperiperi 2020-07-13 11:48:14 +01:00 • committed by GitHub
parent 30d4f752f4
commit d7044b10a2
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15 changed files with 448 additions and 161 deletions
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45
Ryujinx.Tests/Cpu/CpuTest.cs
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@ -167,41 +167,42 @@ namespace Ryujinx.Tests.Cpu
}
}
protected void ExecuteOpcodes()
protected void ExecuteOpcodes(bool runUnicorn = true)
{
_cpuContext.Execute(_context, _entryPoint);
if (_unicornAvailable)
if (_unicornAvailable && runUnicorn)
{
_unicornEmu.RunForCount((_currAddress - _entryPoint - 4) / 4);
}
}
protected ExecutionContext SingleOpcode(uint opcode,
ulong x0 = 0,
ulong x1 = 0,
ulong x2 = 0,
ulong x3 = 0,
ulong x31 = 0,
V128 v0 = default,
V128 v1 = default,
V128 v2 = default,
V128 v3 = default,
V128 v4 = default,
V128 v5 = default,
V128 v30 = default,
V128 v31 = default,
bool overflow = false,
bool carry = false,
bool zero = false,
bool negative = false,
int fpcr = 0,
int fpsr = 0)
ulong x0 = 0,
ulong x1 = 0,
ulong x2 = 0,
ulong x3 = 0,
ulong x31 = 0,
V128 v0 = default,
V128 v1 = default,
V128 v2 = default,
V128 v3 = default,
V128 v4 = default,
V128 v5 = default,
V128 v30 = default,
V128 v31 = default,
bool overflow = false,
bool carry = false,
bool zero = false,
bool negative = false,
int fpcr = 0,
int fpsr = 0,
bool runUnicorn = true)
{
Opcode(opcode);
Opcode(0xD65F03C0); // RET
SetContext(x0, x1, x2, x3, x31, v0, v1, v2, v3, v4, v5, v30, v31, overflow, carry, zero, negative, fpcr, fpsr);
ExecuteOpcodes();
ExecuteOpcodes(runUnicorn);
return GetContext();
}