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Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)

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* Add CRC32 A32 instructions.

* Fix CRC32 instructions.

* Add CRC intrinsic and fast path.

Loop is currently unrolled, will look into adding temp vars after tests are added.

* Begin work on Crc tests

* Fix SSE4.2 path for CRC32C, finialize tests.

* Remove unused IR path.

* Fix spacing between prefix checks.

* This should be Src.

* PTC Version

* OpCodeTable Order

* Integer check improvement. Value and Crc can be either 32 or 64 size.

* This wasn't necessary...

* If size is 3, value type must be I64.

* Fix same src+dest handling for non crc intrinsics.

* Pre-fix (ha) issue with vex encodings
This commit is contained in:
riperiperi 2020-07-13 11:48:14 +01:00 • committed by GitHub
parent 30d4f752f4
commit d7044b10a2
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15 changed files with 448 additions and 161 deletions
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11
ARMeilleure/CodeGen/X86/PreAllocator.cs
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@ -1294,11 +1294,22 @@ namespace ARMeilleure.CodeGen.X86
case Instruction.VectorInsert16:
case Instruction.VectorInsert8:
return !HardwareCapabilities.SupportsVexEncoding;
case Instruction.Extended:
return IsIntrinsicSameOperandDestSrc1(operation);
}
return IsVexSameOperandDestSrc1(operation);
}
private static bool IsIntrinsicSameOperandDestSrc1(Operation operation)
{
IntrinsicOperation intrinOp = (IntrinsicOperation)operation;
IntrinsicInfo info = IntrinsicTable.GetInfo(intrinOp.Intrinsic);
return info.Type == IntrinsicType.Crc32 || IsVexSameOperandDestSrc1(operation);
}
private static bool IsVexSameOperandDestSrc1(Operation operation)
{
if (IsIntrinsic(operation.Instruction))