Move a few more SIMD instructions to emit CIL directly instead of a method call
This commit is contained in:
gdkchan
parent
12e263f8b2
commit
ccc9ce1908
7 changed files with 207 additions and 324 deletions
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@ -102,80 +102,10 @@ namespace ChocolArm64.Instruction
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public static void Eor_V(AILEmitterCtx Context) => EmitVectorBinaryZx(Context, OpCodes.Xor);
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public static void Fadd_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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public static void Fadd_V(AILEmitterCtx Context) => EmitVectorBinaryFOp(Context, OpCodes.Add);
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdvec(Op.Rm);
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Context.EmitLdc_I4(Op.SizeF);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Fadd64),
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nameof(ASoftFallback.Fadd128));
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Context.EmitStvec(Op.Rd);
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}
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public static void Fcvtzs_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdc_I4(0);
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Context.EmitLdc_I4(Op.SizeF);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Fcvtzs_V64),
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nameof(ASoftFallback.Fcvtzs_V128));
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Context.EmitStvec(Op.Rd);
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}
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public static void Fcvtzs_V_Fix(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdc_I4((8 << (Op.Size + 1)) - Op.Imm);
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Context.EmitLdc_I4(Op.Size - 2);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Fcvtzs_V64),
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nameof(ASoftFallback.Fcvtzs_V128));
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Context.EmitStvec(Op.Rd);
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}
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public static void Fcvtzu_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdc_I4(0);
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Context.EmitLdc_I4(Op.SizeF);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Fcvtzu_V_64),
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nameof(ASoftFallback.Fcvtzu_V_128));
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Context.EmitStvec(Op.Rd);
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}
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public static void Fcvtzu_V_Fix(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdc_I4((8 << (Op.Size + 1)) - Op.Imm);
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Context.EmitLdc_I4(Op.Size - 2);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Fcvtzu_V_64),
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nameof(ASoftFallback.Fcvtzu_V_128));
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Context.EmitStvec(Op.Rd);
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}
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public static void Fcvtzs_V(AILEmitterCtx Context) => EmitVectorFcvtS(Context);
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public static void Fcvtzu_V(AILEmitterCtx Context) => EmitVectorFcvtU(Context);
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public static void Fmla_V(AILEmitterCtx Context)
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{
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@ -224,20 +154,7 @@ namespace ChocolArm64.Instruction
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Context.EmitStvec(Op.Rd);
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}
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public static void Fmul_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdvec(Op.Rm);
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Context.EmitLdc_I4(Op.SizeF);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Fmul64),
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nameof(ASoftFallback.Fmul128));
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Context.EmitStvec(Op.Rd);
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}
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public static void Fmul_V(AILEmitterCtx Context) => EmitVectorBinaryFOp(Context, OpCodes.Mul);
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public static void Fmul_Vs(AILEmitterCtx Context)
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{
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@ -255,20 +172,7 @@ namespace ChocolArm64.Instruction
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Context.EmitStvec(Op.Rd);
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}
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public static void Fsub_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdvec(Op.Rm);
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Context.EmitLdc_I4(Op.SizeF);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Fsub64),
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nameof(ASoftFallback.Fsub128));
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Context.EmitStvec(Op.Rd);
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}
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public static void Fsub_V(AILEmitterCtx Context) => EmitVectorBinaryFOp(Context, OpCodes.Sub);
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public static void Ins_Gp(AILEmitterCtx Context)
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{
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@ -870,6 +774,114 @@ namespace ChocolArm64.Instruction
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});
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}
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private static void EmitVectorFcvtS(AILEmitterCtx Context)
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{
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EmitVectorCvtOp(Context, CvtDir.Fcvt, true);
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}
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private static void EmitVectorFcvtU(AILEmitterCtx Context)
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{
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EmitVectorCvtOp(Context, CvtDir.Fcvt, false);
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}
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private static void EmitVectorCvtfS(AILEmitterCtx Context)
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{
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EmitVectorCvtOp(Context, CvtDir.Cvtf, true);
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}
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private static void EmitVectorCvtfU(AILEmitterCtx Context)
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{
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EmitVectorCvtOp(Context, CvtDir.Cvtf, false);
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}
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private enum CvtDir
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{
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Fcvt,
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Cvtf
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}
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private static void EmitVectorCvtOp(AILEmitterCtx Context, CvtDir Dir, bool Signed)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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int SizeI = SizeF + 2;
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int FBits = 0;
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if (Op is AOpCodeSimdShImm OpImm)
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{
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FBits = (8 << (Op.Size + 1)) - OpImm.Imm;
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}
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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for (int Index = 0; Index < (Bytes >> SizeI); Index++)
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{
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EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
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Context.EmitLdc_I4(FBits);
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if (Dir == CvtDir.Fcvt)
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{
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//Float to Integer.
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if (SizeF == 0)
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{
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ASoftFallback.EmitCall(Context, Signed
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? nameof(ASoftFallback.SatSingleToInt32)
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: nameof(ASoftFallback.SatSingleToUInt32));
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}
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else if (SizeF == 1)
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{
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ASoftFallback.EmitCall(Context, Signed
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? nameof(ASoftFallback.SatDoubleToInt64)
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: nameof(ASoftFallback.SatDoubleToUInt64));
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}
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}
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else if (Dir == CvtDir.Cvtf)
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{
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//Integer to Float.
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//TODO.
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}
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EmitVectorInsert(Context, Op.Rd, Index, SizeI);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static void EmitVectorBinaryFOp(AILEmitterCtx Context, OpCode ILOp)
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{
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EmitVectorBinaryFOp(Context, () => Context.Emit(ILOp));
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}
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private static void EmitVectorBinaryFOp(AILEmitterCtx Context, Action Emit)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int SizeF = Op.Size & 1;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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for (int Index = 0; Index < (Bytes >> SizeF + 2); Index++)
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{
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EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
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EmitVectorExtractF(Context, Op.Rm, Index, SizeF);
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Emit();
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EmitVectorInsertF(Context, Op.Rd, Index, SizeF);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static void EmitVectorUnarySx(AILEmitterCtx Context, OpCode ILOp)
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{
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EmitVectorUnarySx(Context, () => Context.Emit(ILOp));
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@ -1047,6 +1059,25 @@ namespace ChocolArm64.Instruction
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}
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}
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private static void EmitVectorExtractF(AILEmitterCtx Context, int Reg, int Index, int Size)
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{
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Context.EmitLdvec(Reg);
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Context.EmitLdc_I4(Index);
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if (Size == 0)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorExtractSingle));
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}
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else if (Size == 1)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorExtractDouble));
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}
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else
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{
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throw new ArgumentOutOfRangeException(nameof(Size));
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}
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}
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private static void EmitVectorExtractSx(AILEmitterCtx Context, int Reg, int Index)
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{
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EmitVectorExtract(Context, Reg, Index, true);
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@ -1070,6 +1101,27 @@ namespace ChocolArm64.Instruction
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: nameof(ASoftFallback.ExtractVec));
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}
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private static void EmitVectorInsertF(AILEmitterCtx Context, int Reg, int Index, int Size)
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{
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Context.EmitLdvec(Reg);
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Context.EmitLdc_I4(Index);
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if (Size == 0)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorInsertSingle));
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}
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else if (Size == 1)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorInsertDouble));
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}
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else
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{
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throw new ArgumentOutOfRangeException(nameof(Size));
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}
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Context.EmitStvec(Reg);
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}
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private static void EmitVectorZeroLower(AILEmitterCtx Context, int Rd)
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{
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EmitVectorInsert(Context, Rd, 0, 3, 0);
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@ -1080,6 +1132,17 @@ namespace ChocolArm64.Instruction
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EmitVectorInsert(Context, Rd, 1, 3, 0);
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}
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private static void EmitVectorInsert(AILEmitterCtx Context, int Reg, int Index, int Size)
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{
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Context.EmitLdvec(Reg);
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Context.EmitLdc_I4(Index);
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Context.EmitLdc_I4(Size);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorInsertInt));
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Context.EmitStvec(Reg);
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}
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private static void EmitVectorInsert(AILEmitterCtx Context, int Reg, int Index, int Size, long Value)
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{
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Context.EmitLdvec(Reg);
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