Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; add 14 Tests. Add 6 Tests for PR#405. Add 2 Tests for PR#412. (#409)
* Update AOpCodeTable.cs * Update AInstEmitSimdShift.cs * Update CpuTestSimdShImm.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Create CpuTestSimdIns.cs * Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update CpuTest.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs
This commit is contained in:
LDj3SNuD
gdkchan
parent
8a78a703f2
commit
c7387be0d2
9 changed files with 1254 additions and 303 deletions
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@ -4,6 +4,7 @@ using ChocolArm64.State;
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using NUnit.Framework;
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using System.Collections.Generic;
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using System.Runtime.Intrinsics;
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namespace Ryujinx.Tests.Cpu
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@ -13,7 +14,7 @@ namespace Ryujinx.Tests.Cpu
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{
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#if Simd
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#region "ValueSource"
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#region "ValueSource (Types)"
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private static ulong[] _1B1H1S1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x000000000000007Ful,
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@ -78,78 +79,183 @@ namespace Ryujinx.Tests.Cpu
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _1S_F_()
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private static IEnumerable<ulong> _1S_F_()
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{
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return new ulong[]
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yield return 0x00000000FF7FFFFFul; // -Max Normal (float.MinValue)
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yield return 0x0000000080800000ul; // -Min Normal
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yield return 0x00000000807FFFFFul; // -Max SubNormal
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yield return 0x0000000080000001ul; // -Min SubNormal
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yield return 0x000000007F7FFFFFul; // +Max Normal (float.MaxValue)
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yield return 0x0000000000800000ul; // +Min Normal
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yield return 0x00000000007FFFFFul; // +Max SubNormal
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yield return 0x0000000000000001ul; // +Min SubNormal
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if (!NoZeros)
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{
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0x00000000FFFFFFFFul, // -QNaN (all ones payload)
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0x00000000FFBFFFFFul, // -SNaN (all ones payload)
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0x00000000FF800000ul, // -INF
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0x00000000FF7FFFFFul, // -Max Normal, float.MinValue
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0x0000000080800000ul, // -Min Normal
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0x00000000807FFFFFul, // -Max SubNormal
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0x0000000080000001ul, // -Min SubNormal
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0x0000000080000000ul, // -0
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0x0000000000000000ul, // +0
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0x0000000000000001ul, // +Min SubNormal
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0x00000000007FFFFFul, // +Max SubNormal
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0x0000000000800000ul, // +Min Normal
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0x000000007F7FFFFFul, // +Max Normal, float.MaxValue
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0x000000007F800000ul, // +INF
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0x000000007FBFFFFFul, // +SNaN (all ones payload)
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0x000000007FFFFFFFul // +QNaN (all ones payload)
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yield return 0x0000000080000000ul; // -Zero
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yield return 0x0000000000000000ul; // +Zero
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}
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if (!NoInfs)
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{
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yield return 0x00000000FF800000ul; // -Infinity
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yield return 0x000000007F800000ul; // +Infinity
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}
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if (!NoNaNs)
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{
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yield return 0x00000000FFFFFFFFul; // -QNaN (all ones payload)
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yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload)
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yield return 0x000000007FFFFFFFul; // +QNaN (all ones payload)
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yield return 0x000000007FBFFFFFul; // +SNaN (all ones payload)
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}
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for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
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{
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ulong Grbg = TestContext.CurrentContext.Random.NextUInt();
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ulong Rnd1 = GenNormal_S();
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ulong Rnd2 = GenSubNormal_S();
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yield return (Grbg << 32) | Rnd1;
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yield return (Grbg << 32) | Rnd2;
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}
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}
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private static IEnumerable<ulong> _2S_F_()
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{
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yield return 0xFF7FFFFFFF7FFFFFul; // -Max Normal (float.MinValue)
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yield return 0x8080000080800000ul; // -Min Normal
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yield return 0x807FFFFF807FFFFFul; // -Max SubNormal
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yield return 0x8000000180000001ul; // -Min SubNormal
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yield return 0x7F7FFFFF7F7FFFFFul; // +Max Normal (float.MaxValue)
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yield return 0x0080000000800000ul; // +Min Normal
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yield return 0x007FFFFF007FFFFFul; // +Max SubNormal
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yield return 0x0000000100000001ul; // +Min SubNormal
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if (!NoZeros)
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{
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yield return 0x8000000080000000ul; // -Zero
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yield return 0x0000000000000000ul; // +Zero
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}
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if (!NoInfs)
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{
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yield return 0xFF800000FF800000ul; // -Infinity
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yield return 0x7F8000007F800000ul; // +Infinity
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}
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if (!NoNaNs)
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{
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yield return 0xFFFFFFFFFFFFFFFFul; // -QNaN (all ones payload)
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yield return 0xFFBFFFFFFFBFFFFFul; // -SNaN (all ones payload)
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yield return 0x7FFFFFFF7FFFFFFFul; // +QNaN (all ones payload)
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yield return 0x7FBFFFFF7FBFFFFFul; // +SNaN (all ones payload)
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}
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for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
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{
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ulong Rnd1 = GenNormal_S();
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ulong Rnd2 = GenSubNormal_S();
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yield return (Rnd1 << 32) | Rnd1;
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yield return (Rnd2 << 32) | Rnd2;
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}
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}
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private static IEnumerable<ulong> _1D_F_()
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{
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yield return 0xFFEFFFFFFFFFFFFFul; // -Max Normal (double.MinValue)
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yield return 0x8010000000000000ul; // -Min Normal
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yield return 0x800FFFFFFFFFFFFFul; // -Max SubNormal
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yield return 0x8000000000000001ul; // -Min SubNormal
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yield return 0x7FEFFFFFFFFFFFFFul; // +Max Normal (double.MaxValue)
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yield return 0x0010000000000000ul; // +Min Normal
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yield return 0x000FFFFFFFFFFFFFul; // +Max SubNormal
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yield return 0x0000000000000001ul; // +Min SubNormal
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if (!NoZeros)
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{
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yield return 0x8000000000000000ul; // -Zero
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yield return 0x0000000000000000ul; // +Zero
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}
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if (!NoInfs)
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{
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yield return 0xFFF0000000000000ul; // -Infinity
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yield return 0x7FF0000000000000ul; // +Infinity
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}
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if (!NoNaNs)
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{
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yield return 0xFFFFFFFFFFFFFFFFul; // -QNaN (all ones payload)
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yield return 0xFFF7FFFFFFFFFFFFul; // -SNaN (all ones payload)
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yield return 0x7FFFFFFFFFFFFFFFul; // +QNaN (all ones payload)
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yield return 0x7FF7FFFFFFFFFFFFul; // +SNaN (all ones payload)
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}
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for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
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{
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ulong Rnd1 = GenNormal_D();
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ulong Rnd2 = GenSubNormal_D();
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yield return Rnd1;
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yield return Rnd2;
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}
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}
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _F_Cvt_NZ_SU_S_S_()
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{
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return new uint[]
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{
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0x5E21A820u, // FCVTNS S0, S1
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0x7E21A820u, // FCVTNU S0, S1
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0x5EA1B820u, // FCVTZS S0, S1
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0x7EA1B820u // FCVTZU S0, S1
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};
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}
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private static ulong[] _2S_F_()
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private static uint[] _F_Cvt_NZ_SU_S_D_()
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{
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return new ulong[]
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return new uint[]
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{
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0xFFFFFFFFFFFFFFFFul, // -QNaN (all ones payload)
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0xFFBFFFFFFFBFFFFFul, // -SNaN (all ones payload)
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0xFF800000FF800000ul, // -INF
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0xFF7FFFFFFF7FFFFFul, // -Max Normal, float.MinValue
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0x8080000080800000ul, // -Min Normal
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0x807FFFFF807FFFFFul, // -Max SubNormal
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0x8000000180000001ul, // -Min SubNormal
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0x8000000080000000ul, // -0
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0x0000000000000000ul, // +0
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0x0000000100000001ul, // +Min SubNormal
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0x007FFFFF007FFFFFul, // +Max SubNormal
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0x0080000000800000ul, // +Min Normal
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0x7F7FFFFF7F7FFFFFul, // +Max Normal, float.MaxValue
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0x7F8000007F800000ul, // +INF
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0x7FBFFFFF7FBFFFFFul, // +SNaN (all ones payload)
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0x7FFFFFFF7FFFFFFFul // +QNaN (all ones payload)
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0x5E61A820u, // FCVTNS D0, D1
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0x7E61A820u, // FCVTNU D0, D1
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0x5EE1B820u, // FCVTZS D0, D1
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0x7EE1B820u // FCVTZU D0, D1
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};
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}
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private static ulong[] _1D_F_()
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private static uint[] _F_Cvt_NZ_SU_V_2S_4S_()
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{
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return new ulong[]
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return new uint[]
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{
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0xFFFFFFFFFFFFFFFFul, // -QNaN (all ones payload)
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0xFFF7FFFFFFFFFFFFul, // -SNaN (all ones payload)
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0xFFF0000000000000ul, // -INF
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0xFFEFFFFFFFFFFFFFul, // -Max Normal, double.MinValue
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0x8010000000000000ul, // -Min Normal
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0x800FFFFFFFFFFFFFul, // -Max SubNormal
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0x8000000000000001ul, // -Min SubNormal
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0x8000000000000000ul, // -0
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0x0000000000000000ul, // +0
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0x0000000000000001ul, // +Min SubNormal
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0x000FFFFFFFFFFFFFul, // +Max SubNormal
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0x0010000000000000ul, // +Min Normal
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0x7FEFFFFFFFFFFFFFul, // +Max Normal, double.MaxValue
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0x7FF0000000000000ul, // +INF
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0x7FF7FFFFFFFFFFFFul, // +SNaN (all ones payload)
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0x7FFFFFFFFFFFFFFFul // +QNaN (all ones payload)
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0x0E21A800u, // FCVTNS V0.2S, V0.2S
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0x2E21A800u, // FCVTNU V0.2S, V0.2S
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0x0EA1B800u, // FCVTZS V0.2S, V0.2S
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0x2EA1B800u // FCVTZU V0.2S, V0.2S
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};
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}
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private static uint[] _F_Cvt_NZ_SU_V_2D_()
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{
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return new uint[]
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{
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0x4E61A800u, // FCVTNS V0.2D, V0.2D
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0x6E61A800u, // FCVTNU V0.2D, V0.2D
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0x4EE1B800u, // FCVTZS V0.2D, V0.2D
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0x6EE1B800u // FCVTZU V0.2D, V0.2D
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};
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}
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#endregion
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private const int RndCnt = 2;
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private static readonly bool NoZeros = false;
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private static readonly bool NoInfs = false;
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private static readonly bool NoNaNs = false;
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[Test, Pairwise, Description("ABS <V><d>, <V><n>")]
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public void Abs_S_D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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@ -645,176 +751,104 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("FCVTNS <V><d>, <V><n>")]
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public void Fcvtns_S_S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1S_F_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_1S_F_")] [Random(RndCnt)] ulong A)
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[Test, Pairwise, Description("FCVT <Dd>, <Sn>")]
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public void Fcvt_S_SD([ValueSource("_1S_F_")] ulong A)
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{
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//const int DNFlagBit = 25; // Default NaN mode control bit.
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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uint Opcode = 0x5E21A800; // FCVTNS S0, S0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint Opcode = 0x1E22C020; // FCVT D0, S1
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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ulong Z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> V0 = MakeVectorE1(Z);
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Vector128<float> V1 = MakeVectorE0(A);
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//int Fpcr = 1 << DNFlagBit; // Any operation involving one or more NaNs returns the Default NaN.
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//Fpcr |= 1 << FZFlagBit; // Flush-to-zero mode enabled.
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IOC*/);
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}
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[Test, Pairwise, Description("FCVT <Sd>, <Dn>")]
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public void Fcvt_S_DS([ValueSource("_1D_F_")] ulong A)
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{
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uint Opcode = 0x1E624020; // FCVT S0, D1
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ulong Z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void F_Cvt_NZ_SU_S_S([ValueSource("_F_Cvt_NZ_SU_S_S_")] uint Opcodes,
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[ValueSource("_1S_F_")] ulong A)
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{
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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ulong Z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
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}
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[Test, Pairwise, Description("FCVTNS <V><d>, <V><n>")]
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public void Fcvtns_S_D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_F_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_1D_F_")] [Random(RndCnt)] ulong A)
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[Test, Pairwise]
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public void F_Cvt_NZ_SU_S_D([ValueSource("_F_Cvt_NZ_SU_S_D_")] uint Opcodes,
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[ValueSource("_1D_F_")] ulong A)
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{
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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uint Opcode = 0x5E61A800; // FCVTNS D0, D0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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ulong Z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> V0 = MakeVectorE1(Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
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CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("FCVTNS <Vd>.<T>, <Vn>.<T>")]
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public void Fcvtns_V_2S_4S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_2S_F_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_2S_F_")] [Random(RndCnt)] ulong A,
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[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
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[Test, Pairwise]
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public void F_Cvt_NZ_SU_V_2S_4S([ValueSource("_F_Cvt_NZ_SU_V_2S_4S_")] uint Opcodes,
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[Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_2S_F_")] ulong Z,
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[ValueSource("_2S_F_")] ulong A,
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[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
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{
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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uint Opcode = 0x0E21A800; // FCVTNS V0.2S, V0.2S
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((Q & 1) << 30);
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcodes |= ((Q & 1) << 30);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
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CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("FCVTNS <Vd>.<T>, <Vn>.<T>")]
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public void Fcvtns_V_2D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_F_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_1D_F_")] [Random(RndCnt)] ulong A)
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[Test, Pairwise]
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public void F_Cvt_NZ_SU_V_2D([ValueSource("_F_Cvt_NZ_SU_V_2D_")] uint Opcodes,
|
||||
[Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[ValueSource("_1D_F_")] ulong Z,
|
||||
[ValueSource("_1D_F_")] ulong A)
|
||||
{
|
||||
//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
|
||||
|
||||
uint Opcode = 0x4E61A800; // FCVTNS V0.2D, V0.2D
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
|
||||
//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
|
||||
Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
|
||||
AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
|
||||
|
||||
CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("FCVTNU <V><d>, <V><n>")]
|
||||
public void Fcvtnu_S_S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[ValueSource("_1S_F_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_1S_F_")] [Random(RndCnt)] ulong A)
|
||||
{
|
||||
//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
|
||||
|
||||
uint Opcode = 0x7E21A800; // FCVTNU S0, S0
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
|
||||
//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
|
||||
|
||||
CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("FCVTNU <V><d>, <V><n>")]
|
||||
public void Fcvtnu_S_D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[ValueSource("_1D_F_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_1D_F_")] [Random(RndCnt)] ulong A)
|
||||
{
|
||||
//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
|
||||
|
||||
uint Opcode = 0x7E61A800; // FCVTNU D0, D0
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
|
||||
//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
|
||||
|
||||
CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("FCVTNU <Vd>.<T>, <Vn>.<T>")]
|
||||
public void Fcvtnu_V_2S_4S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[ValueSource("_2S_F_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_2S_F_")] [Random(RndCnt)] ulong A,
|
||||
[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
|
||||
{
|
||||
//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
|
||||
|
||||
uint Opcode = 0x2E21A800; // FCVTNU V0.2S, V0.2S
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((Q & 1) << 30);
|
||||
|
||||
//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
|
||||
|
||||
CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("FCVTNU <Vd>.<T>, <Vn>.<T>")]
|
||||
public void Fcvtnu_V_2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[ValueSource("_1D_F_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_1D_F_")] [Random(RndCnt)] ulong A)
|
||||
{
|
||||
//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
|
||||
|
||||
uint Opcode = 0x6E61A800; // FCVTNU V0.2D, V0.2D
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
|
||||
//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
|
||||
|
||||
CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("NEG <V><d>, <V><n>")]
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue