drashna/ryujinx
1
0
Fork 0
Code Activity Actions

Add ADD (zx imm12), NOP, MOV (rs), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions (#3683)

Browse source 
* Add ADD (zx imm12), NOP, MOV (register shifted), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions, fix LDRD, STRD, CBZ, CBNZ and BLX (reg)

* Bump PPTC version
This commit is contained in:
gdkchan 2022-09-09 22:09:11 -03:00 • committed by GitHub
parent db45688aa8
commit c64524a240
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
16 changed files with 185 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

19
ARMeilleure/Decoders/OpCodeT32ShiftReg.cs Normal file
View file

@ -0,0 +1,19 @@
namespace ARMeilleure.Decoders
{
class OpCodeT32ShiftReg : OpCodeT32Alu, IOpCode32AluRsReg
{
public int Rm => Rn;
public int Rs { get; }
public ShiftType ShiftType { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32ShiftReg(inst, address, opCode);
public OpCodeT32ShiftReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rs = (opCode >> 0) & 0xf;
ShiftType = (ShiftType)((opCode >> 21) & 3);
}
}
}