Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)
* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes * Re-align opcode table * Re-enable undefined, use subclasses to fix checks * Add test and fix VRSHR instruction * PR feedback
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gdkchan
GitHub
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c26f3774bd
14 changed files with 873 additions and 288 deletions
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@ -2,6 +2,7 @@
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System;
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using System.Diagnostics;
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using static ARMeilleure.Instructions.InstEmitFlowHelper;
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using static ARMeilleure.Instructions.InstEmitHelper;
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@ -113,20 +114,13 @@ namespace ARMeilleure.Instructions
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Operand insert = GetIntA32(context, op.Rt);
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// Zero extend into an I64, then replicate. Saves the most time over elementwise inserts.
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switch (op.Size)
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insert = op.Size switch
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{
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case 2:
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insert = context.Multiply(context.ZeroExtend32(OperandType.I64, insert), Const(0x0000000100000001u));
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break;
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case 1:
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insert = context.Multiply(context.ZeroExtend16(OperandType.I64, insert), Const(0x0001000100010001u));
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break;
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case 0:
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insert = context.Multiply(context.ZeroExtend8(OperandType.I64, insert), Const(0x0101010101010101u));
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break;
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default:
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throw new InvalidOperationException("Unknown Vdup Size.");
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}
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2 => context.Multiply(context.ZeroExtend32(OperandType.I64, insert), Const(0x0000000100000001u)),
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1 => context.Multiply(context.ZeroExtend16(OperandType.I64, insert), Const(0x0001000100010001u)),
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0 => context.Multiply(context.ZeroExtend8(OperandType.I64, insert), Const(0x0101010101010101u)),
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_ => throw new InvalidOperationException($"Invalid Vdup size \"{op.Size}\".")
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};
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InsertScalar(context, op.Vd, insert);
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if (op.Q)
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@ -142,20 +136,13 @@ namespace ARMeilleure.Instructions
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Operand insert = EmitVectorExtractZx32(context, op.Vm >> 1, ((op.Vm & 1) << (3 - op.Size)) + op.Index, op.Size);
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// Zero extend into an I64, then replicate. Saves the most time over elementwise inserts.
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switch (op.Size)
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insert = op.Size switch
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{
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case 2:
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insert = context.Multiply(context.ZeroExtend32(OperandType.I64, insert), Const(0x0000000100000001u));
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break;
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case 1:
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insert = context.Multiply(context.ZeroExtend16(OperandType.I64, insert), Const(0x0001000100010001u));
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break;
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case 0:
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insert = context.Multiply(context.ZeroExtend8(OperandType.I64, insert), Const(0x0101010101010101u));
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break;
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default:
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throw new InvalidOperationException("Unknown Vdup Size.");
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}
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2 => context.Multiply(context.ZeroExtend32(OperandType.I64, insert), Const(0x0000000100000001u)),
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1 => context.Multiply(context.ZeroExtend16(OperandType.I64, insert), Const(0x0001000100010001u)),
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0 => context.Multiply(context.ZeroExtend8(OperandType.I64, insert), Const(0x0101010101010101u)),
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_ => throw new InvalidOperationException($"Invalid Vdup size \"{op.Size}\".")
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};
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InsertScalar(context, op.Vd, insert);
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if (op.Q)
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@ -575,75 +562,6 @@ namespace ARMeilleure.Instructions
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}
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}
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public static void Vmul_S(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitScalarBinaryOpF32(context, Intrinsic.X86Mulss, Intrinsic.X86Mulsd);
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}
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else if (Optimizations.FastFP)
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{
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EmitScalarBinaryOpF32(context, (op1, op2) => context.Multiply(op1, op2));
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}
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else
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{
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EmitScalarBinaryOpF32(context, (op1, op2) =>
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{
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return EmitSoftFloatCall(context, SoftFloat32.FPMul, SoftFloat64.FPMul, op1, op2);
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});
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}
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}
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public static void Vmul_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitVectorBinaryOpF32(context, Intrinsic.X86Mulps, Intrinsic.X86Mulpd);
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}
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else if (Optimizations.FastFP)
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{
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EmitVectorBinaryOpF32(context, (op1, op2) => context.Multiply(op1, op2));
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}
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else
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{
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EmitVectorBinaryOpF32(context, (op1, op2) =>
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{
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return EmitSoftFloatCallDefaultFpscr(context, SoftFloat32.FPMulFpscr, SoftFloat64.FPMulFpscr, op1, op2);
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});
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}
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}
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public static void Vmul_I(ArmEmitterContext context)
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{
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if ((context.CurrOp as OpCode32SimdReg).U) throw new NotImplementedException("Polynomial mode not implemented");
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EmitVectorBinaryOpSx32(context, (op1, op2) => context.Multiply(op1, op2));
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}
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public static void Vmul_1(ArmEmitterContext context)
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{
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OpCode32SimdRegElem op = (OpCode32SimdRegElem)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitVectorByScalarOpF32(context, Intrinsic.X86Mulps, Intrinsic.X86Mulpd);
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}
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else if (Optimizations.FastFP)
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{
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EmitVectorByScalarOpF32(context, (op1, op2) => context.Multiply(op1, op2));
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}
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else
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{
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EmitVectorByScalarOpF32(context, (op1, op2) => EmitSoftFloatCallDefaultFpscr(context, SoftFloat32.FPMulFpscr, SoftFloat64.FPMulFpscr, op1, op2));
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}
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}
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else
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{
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EmitVectorByScalarOpI32(context, (op1, op2) => context.Multiply(op1, op2), false);
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}
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}
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public static void Vmla_S(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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@ -786,6 +704,111 @@ namespace ARMeilleure.Instructions
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}
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}
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public static void Vmlsl_I(ArmEmitterContext context)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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EmitVectorTernaryLongOpI32(context, (opD, op1, op2) => context.Subtract(opD, context.Multiply(op1, op2)), !op.U);
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}
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public static void Vmul_S(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitScalarBinaryOpF32(context, Intrinsic.X86Mulss, Intrinsic.X86Mulsd);
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}
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else if (Optimizations.FastFP)
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{
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EmitScalarBinaryOpF32(context, (op1, op2) => context.Multiply(op1, op2));
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}
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else
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{
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EmitScalarBinaryOpF32(context, (op1, op2) =>
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{
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return EmitSoftFloatCall(context, SoftFloat32.FPMul, SoftFloat64.FPMul, op1, op2);
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});
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}
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}
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public static void Vmul_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitVectorBinaryOpF32(context, Intrinsic.X86Mulps, Intrinsic.X86Mulpd);
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}
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else if (Optimizations.FastFP)
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{
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EmitVectorBinaryOpF32(context, (op1, op2) => context.Multiply(op1, op2));
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}
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else
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{
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EmitVectorBinaryOpF32(context, (op1, op2) =>
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{
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return EmitSoftFloatCallDefaultFpscr(context, SoftFloat32.FPMulFpscr, SoftFloat64.FPMulFpscr, op1, op2);
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});
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}
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}
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public static void Vmul_I(ArmEmitterContext context)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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if (op.U) // This instruction is always signed, U indicates polynomial mode.
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{
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EmitVectorBinaryOpZx32(context, (op1, op2) => EmitPolynomialMultiply(context, op1, op2, 8 << op.Size));
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}
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else
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{
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EmitVectorBinaryOpSx32(context, (op1, op2) => context.Multiply(op1, op2));
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}
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}
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public static void Vmul_1(ArmEmitterContext context)
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{
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OpCode32SimdRegElem op = (OpCode32SimdRegElem)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitVectorByScalarOpF32(context, Intrinsic.X86Mulps, Intrinsic.X86Mulpd);
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}
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else if (Optimizations.FastFP)
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{
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EmitVectorByScalarOpF32(context, (op1, op2) => context.Multiply(op1, op2));
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}
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else
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{
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EmitVectorByScalarOpF32(context, (op1, op2) => EmitSoftFloatCallDefaultFpscr(context, SoftFloat32.FPMulFpscr, SoftFloat64.FPMulFpscr, op1, op2));
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}
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}
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else
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{
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EmitVectorByScalarOpI32(context, (op1, op2) => context.Multiply(op1, op2), false);
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}
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}
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public static void Vmull_1(ArmEmitterContext context)
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{
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OpCode32SimdRegElem op = (OpCode32SimdRegElem)context.CurrOp;
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EmitVectorByScalarLongOpI32(context, (op1, op2) => context.Multiply(op1, op2), !op.U);
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}
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public static void Vmull_I(ArmEmitterContext context)
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{
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OpCode32SimdRegLong op = (OpCode32SimdRegLong)context.CurrOp;
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if (op.Polynomial)
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{
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EmitVectorBinaryLongOpI32(context, (op1, op2) => EmitPolynomialMultiply(context, op1, op2, 8 << op.Size), false);
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}
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else
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{
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EmitVectorBinaryLongOpI32(context, (op1, op2) => context.Multiply(op1, op2), !op.U);
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}
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}
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public static void Vpadd_V(ArmEmitterContext context)
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{
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if (Optimizations.FastFP && Optimizations.UseSse2)
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@ -1157,5 +1180,27 @@ namespace ARMeilleure.Instructions
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EmitVectorBinaryOpSimd32(context, genericEmit);
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}
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}
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private static Operand EmitPolynomialMultiply(ArmEmitterContext context, Operand op1, Operand op2, int eSize)
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{
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Debug.Assert(eSize <= 32);
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Operand result = eSize == 32 ? Const(0L) : Const(0);
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if (eSize == 32)
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{
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op1 = context.ZeroExtend32(OperandType.I64, op1);
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op2 = context.ZeroExtend32(OperandType.I64, op2);
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}
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for (int i = 0; i < eSize; i++)
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{
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Operand mask = context.BitwiseAnd(op1, Const(op1.Type, 1L << i));
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result = context.BitwiseExclusiveOr(result, context.Multiply(op2, mask));
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}
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return result;
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}
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}
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}
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