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Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)

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* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes

* Re-align opcode table

* Re-enable undefined, use subclasses to fix checks

* Add test and fix VRSHR instruction

* PR feedback
This commit is contained in:
gdkchan 2020-03-10 21:49:27 -03:00 • committed by GitHub
parent 89ccec197e
commit c26f3774bd
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GPG key ID: 4AEE18F83AFDEB23
14 changed files with 873 additions and 288 deletions
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13
ARMeilleure/Decoders/OpCode32SimdRegElem.cs
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@ -6,13 +6,20 @@
{
Q = ((opCode >> 24) & 0x1) != 0;
F = ((opCode >> 8) & 0x1) != 0;
Size = ((opCode >> 20) & 0x3);
Size = (opCode >> 20) & 0x3;
RegisterSize = Q ? RegisterSize.Simd128 : RegisterSize.Simd64;
Vm = ((opCode >> 5) & 0x1) | ((opCode << 1) & 0x1e);
if (Size == 1)
{
Vm = ((opCode >> 3) & 0x1) | ((opCode >> 4) & 0x2) | ((opCode << 2) & 0x1c);
}
else /* if (Size == 2) */
{
Vm = ((opCode >> 5) & 0x1) | ((opCode << 1) & 0x1e);
}
if (DecoderHelper.VectorArgumentsInvalid(Q, Vd, Vn) || Size == 0 || (Size == 1 && F))
if (GetType() == typeof(OpCode32SimdRegElem) && DecoderHelper.VectorArgumentsInvalid(Q, Vd, Vn) || Size == 0 || (Size == 1 && F))
{
Instruction = InstDescriptor.Undefined;
}