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Implement some ARM32 memory instructions and CMP (#565)

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* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)

* Rename some opcode classes and flag masks for consistency

* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations

* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC

* Re-align arm32 instructions on the opcode table
This commit is contained in:
gdkchan 2019-01-29 13:06:11 -03:00 • committed by GitHub
parent 8f7fcede7f
commit c1bdf19061
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GPG key ID: 4AEE18F83AFDEB23
29 changed files with 686 additions and 87 deletions
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23
ChocolArm64/Instructions/InstEmitFlow32.cs
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@ -11,7 +11,7 @@ namespace ChocolArm64.Instructions
{
public static void B(ILEmitterCtx context)
{
IOpCodeBImm32 op = (IOpCodeBImm32)context.CurrOp;
IOpCode32BImm op = (IOpCode32BImm)context.CurrOp;
if (context.CurrBlock.Branch != null)
{
@ -38,7 +38,7 @@ namespace ChocolArm64.Instructions
public static void Bx(ILEmitterCtx context)
{
IOpCodeBReg32 op = (IOpCodeBReg32)context.CurrOp;
IOpCode32BReg op = (IOpCode32BReg)context.CurrOp;
context.EmitStoreState();
@ -49,7 +49,7 @@ namespace ChocolArm64.Instructions
private static void Blx(ILEmitterCtx context, bool x)
{
IOpCodeBImm32 op = (IOpCodeBImm32)context.CurrOp;
IOpCode32BImm op = (IOpCode32BImm)context.CurrOp;
uint pc = op.GetPc();
@ -78,22 +78,5 @@ namespace ChocolArm64.Instructions
InstEmitFlowHelper.EmitCall(context, op.Imm);
}
private static void EmitBxWritePc(ILEmitterCtx context)
{
context.Emit(OpCodes.Dup);
context.EmitLdc_I4(1);
context.Emit(OpCodes.And);
context.EmitStflg((int)PState.TBit);
context.EmitLdc_I4(~1);
context.Emit(OpCodes.And);
context.Emit(OpCodes.Conv_U8);
context.Emit(OpCodes.Ret);
}
}
}