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gdkchan 2018-02-04 20:08:20 -03:00
commit b7e1d9930d
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Ryujinx/Cpu/Decoder/AOpCodeSimdFcond.cs Normal file
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using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class AOpCodeSimdFcond : AOpCodeSimdReg, IAOpCodeCond
{
public int NZCV { get; private set; }
public ACond Cond { get; private set; }
public AOpCodeSimdFcond(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
NZCV = (OpCode >> 0) & 0xf;
Cond = (ACond)((OpCode >> 12) & 0xf);
}
}
}