CPU: Implement VFNMS.F32/64 (#1758)
* Add necessary methods / op-code * Enable Support for FMA Instruction Set * Add Intrinsics / Assembly Opcodes for VFMSUB231XX. * Add X86 Instructions for VFMSUB231XX * Implement VFNMS * Implement VFNMS Tests * Add special cases for FMA instructions. * Update PPTC Version * Remove unused Op * Move Check into Assert / Cleanup * Rename and cleanup * Whitespace * Whitespace / Rename * Re-sort * Address final requests * Implement VFMA.F64 * Simplify switch * Simplify FMA Instructions into their own IntrinsicType. * Remove whitespace * Fix indentation * Change tests for Vfnms -- disable inf / nan * Move args up, not description ;) * Undo vfma * Completely remove vfms code., * Fix order of instruction in assembler
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14 changed files with 462 additions and 363 deletions
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@ -284,6 +284,21 @@ namespace ARMeilleure.Instructions
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}
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}
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public static void Vfnms_S(ArmEmitterContext context) // Fused.
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{
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if (Optimizations.FastFP && Optimizations.UseFma)
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{
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EmitScalarTernaryOpF32(context, Intrinsic.X86Vfmsub231ss, Intrinsic.X86Vfmsub231sd);
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}
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else
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{
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EmitScalarTernaryOpF32(context, (op1, op2, op3) =>
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{
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return EmitSoftFloatCall(context, nameof(SoftFloat32.FPMulAdd), context.Negate(op1), op2, op3);
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});
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}
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}
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public static void Vhadd(ArmEmitterContext context)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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@ -901,6 +901,20 @@ namespace ARMeilleure.Instructions
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context.Copy(initialD, res);
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}
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public static void EmitScalarTernaryOpF32(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64)
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{
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OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp;
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bool doubleSize = (op.Size & 1) != 0;
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Intrinsic inst = doubleSize ? inst64 : inst32;
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EmitScalarTernaryOpSimd32(context, (d, n, m) =>
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{
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return context.AddIntrinsic(inst, d, n, m);
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});
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}
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public static void EmitScalarTernaryOpF32(ArmEmitterContext context, Intrinsic inst32pt1, Intrinsic inst64pt1, Intrinsic inst32pt2, Intrinsic inst64pt2)
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{
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OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp;
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@ -571,6 +571,7 @@ namespace ARMeilleure.Instructions
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Vext,
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Vfma,
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Vfms,
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Vfnms,
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Vhadd,
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Vld1,
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Vld2,
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