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Fix Sshl_V; Add S/Uqrshl_V, S/Uqshl_V, S/Urshl_V; Add Tests. (#516)

Browse source 
* Update OpCodeTable.cs

* Update InstEmitSimdShift.cs

* Update SoftFallback.cs

* Update CpuTestSimdReg.cs

* Nit.

* Update SoftFallback.cs

* Update Optimizations.cs

* Update InstEmitSimdLogical.cs

* Update InstEmitSimdArithmetic.cs
This commit is contained in:
LDj3SNuD 2018-12-02 01:34:43 +01:00 • committed by gdkchan
parent 9b22e8af5e
commit ad00fd0244
8 changed files with 790 additions and 132 deletions
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29
ChocolArm64/Instructions/InstEmitSimdArithmetic.cs
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@ -1638,7 +1638,34 @@ namespace ChocolArm64.Instructions
public static void Neg_V(ILEmitterCtx context)
{
EmitVectorUnaryOpSx(context, () => context.Emit(OpCodes.Neg));
if (Optimizations.UseSse2)
{
OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
Type[] typesSub = new Type[] { VectorIntTypesPerSizeLog2[op.Size], VectorIntTypesPerSizeLog2[op.Size] };
string[] namesSzv = new string[] { nameof(VectorHelper.VectorSByteZero),
nameof(VectorHelper.VectorInt16Zero),
nameof(VectorHelper.VectorInt32Zero),
nameof(VectorHelper.VectorInt64Zero) };
VectorHelper.EmitCall(context, namesSzv[op.Size]);
EmitLdvecWithSignedCast(context, op.Rn, op.Size);
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Subtract), typesSub));
EmitStvecWithSignedCast(context, op.Rd, op.Size);
if (op.RegisterSize == RegisterSize.Simd64)
{
EmitVectorZeroUpper(context, op.Rd);
}
}
else
{
EmitVectorUnaryOpSx(context, () => context.Emit(OpCodes.Neg));
}
}
public static void Raddhn_V(ILEmitterCtx context)