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Add a new JIT compiler for CPU code (#693)

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* Start of the ARMeilleure project

* Refactoring around the old IRAdapter, now renamed to PreAllocator

* Optimize the LowestBitSet method

* Add CLZ support and fix CLS implementation

* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks

* Implement the ByteSwap IR instruction, and some refactoring on the assembler

* Implement the DivideUI IR instruction and fix 64-bits IDIV

* Correct constant operand type on CSINC

* Move division instructions implementation to InstEmitDiv

* Fix destination type for the ConditionalSelect IR instruction

* Implement UMULH and SMULH, with new IR instructions

* Fix some issues with shift instructions

* Fix constant types for BFM instructions

* Fix up new tests using the new V128 struct

* Update tests

* Move DIV tests to a separate file

* Add support for calls, and some instructions that depends on them

* Start adding support for SIMD & FP types, along with some of the related ARM instructions

* Fix some typos and the divide instruction with FP operands

* Fix wrong method call on Clz_V

* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes

* Implement SIMD logical instructions and more misc. fixes

* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations

* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes

* Implement SIMD shift instruction and fix Dup_V

* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table

* Fix check with tolerance on tester

* Implement FP & SIMD comparison instructions, and some fixes

* Update FCVT (Scalar) encoding on the table to support the Half-float variants

* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes

* Use old memory access methods, made a start on SIMD memory insts support, some fixes

* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes

* Fix arguments count with struct return values, other fixes

* More instructions

* Misc. fixes and integrate LDj3SNuD fixes

* Update tests

* Add a faster linear scan allocator, unwinding support on windows, and other changes

* Update Ryujinx.HLE

* Update Ryujinx.Graphics

* Fix V128 return pointer passing, RCX is clobbered

* Update Ryujinx.Tests

* Update ITimeZoneService

* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks

* Use generic GetFunctionPointerForDelegate method and other tweaks

* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics

* Remove some unused code on the assembler

* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler

* Add hardware capability detection

* Fix regression on Sha1h and revert Fcm** changes

* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator

* Fix silly mistake introduced on last commit on CpuId

* Generate inline stack probes when the stack allocation is too large

* Initial support for the System-V ABI

* Support multiple destination operands

* Fix SSE2 VectorInsert8 path, and other fixes

* Change placement of XMM callee save and restore code to match other compilers

* Rename Dest to Destination and Inst to Instruction

* Fix a regression related to calls and the V128 type

* Add an extra space on comments to match code style

* Some refactoring

* Fix vector insert FP32 SSE2 path

* Port over the ARM32 instructions

* Avoid memory protection races on JIT Cache

* Another fix on VectorInsert FP32 (thanks to LDj3SNuD

* Float operands don't need to use the same register when VEX is supported

* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks

* Some nits, small improvements on the pre allocator

* CpuThreadState is gone

* Allow changing CPU emulators with a config entry

* Add runtime identifiers on the ARMeilleure project

* Allow switching between CPUs through a config entry (pt. 2)

* Change win10-x64 to win-x64 on projects

* Update the Ryujinx project to use ARMeilleure

* Ensure that the selected register is valid on the hybrid allocator

* Allow exiting on returns to 0 (should fix test regression)

* Remove register assignments for most used variables on the hybrid allocator

* Do not use fixed registers as spill temp

* Add missing namespace and remove unneeded using

* Address PR feedback

* Fix types, etc

* Enable AssumeStrictAbiCompliance by default

* Ensure that Spill and Fill don't load or store any more than necessary
This commit is contained in:
gdkchan 2019-08-08 15:56:22 -03:00 • committed by emmauss
parent 1ba58e9942
commit a731ab3a2a
310 changed files with 37389 additions and 2086 deletions
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59
Ryujinx.HLE/HOS/Kernel/SupervisorCall/SvcTable.cs
View file

@ -1,4 +1,4 @@
using ChocolArm64.State;
using ARMeilleure.State;
using Ryujinx.Common.Logging;
using Ryujinx.HLE.HOS.Kernel.Common;
using System;
@ -14,7 +14,7 @@ namespace Ryujinx.HLE.HOS.Kernel.SupervisorCall
private static Dictionary<int, string> _svcFuncs64;
private static Action<SvcHandler, CpuThreadState>[] _svcTable64;
private static Action<SvcHandler, IExecutionContext>[] _svcTable64;
static SvcTable()
{
@ -77,10 +77,10 @@ namespace Ryujinx.HLE.HOS.Kernel.SupervisorCall
{ 0x78, nameof(SvcHandler.UnmapProcessCodeMemory64) }
};
_svcTable64 = new Action<SvcHandler, CpuThreadState>[0x80];
_svcTable64 = new Action<SvcHandler, IExecutionContext>[0x80];
}
public static Action<SvcHandler, CpuThreadState> GetSvcFunc(int svcId)
public static Action<SvcHandler, IExecutionContext> GetSvcFunc(int svcId)
{
if (_svcTable64[svcId] != null)
{
@ -95,9 +95,9 @@ namespace Ryujinx.HLE.HOS.Kernel.SupervisorCall
return null;
}
private static Action<SvcHandler, CpuThreadState> GenerateMethod(string svcName)
private static Action<SvcHandler, IExecutionContext> GenerateMethod(string svcName)
{
Type[] argTypes = new Type[] { typeof(SvcHandler), typeof(CpuThreadState) };
Type[] argTypes = new Type[] { typeof(SvcHandler), typeof(IExecutionContext) };
DynamicMethod method = new DynamicMethod(svcName, null, argTypes);
@ -183,7 +183,11 @@ namespace Ryujinx.HLE.HOS.Kernel.SupervisorCall
generator.Emit(OpCodes.Conv_I);
generator.Emit(OpCodes.Ldarg_1);
generator.Emit(OpCodes.Ldfld, GetStateFieldX(byRefArgsCount + index));
generator.Emit(OpCodes.Ldc_I4, byRefArgsCount + index);
MethodInfo info = typeof(IExecutionContext).GetMethod(nameof(IExecutionContext.GetX));
generator.Emit(OpCodes.Call, info);
generator.Emit(OpCodes.Box, typeof(ulong));
@ -227,7 +231,11 @@ namespace Ryujinx.HLE.HOS.Kernel.SupervisorCall
else
{
generator.Emit(OpCodes.Ldarg_1);
generator.Emit(OpCodes.Ldfld, GetStateFieldX(byRefArgsCount + index));
generator.Emit(OpCodes.Ldc_I4, byRefArgsCount + index);
MethodInfo info = typeof(IExecutionContext).GetMethod(nameof(IExecutionContext.GetX));
generator.Emit(OpCodes.Call, info);
ConvertToArgType(argType);
}
@ -258,51 +266,44 @@ namespace Ryujinx.HLE.HOS.Kernel.SupervisorCall
generator.Emit(OpCodes.Stloc, tempLocal);
generator.Emit(OpCodes.Ldarg_1);
generator.Emit(OpCodes.Ldc_I4, outRegIndex++);
generator.Emit(OpCodes.Ldloc, tempLocal);
ConvertToFieldType(retType);
generator.Emit(OpCodes.Stfld, GetStateFieldX(outRegIndex++));
MethodInfo info = typeof(IExecutionContext).GetMethod(nameof(IExecutionContext.SetX));
generator.Emit(OpCodes.Call, info);
}
for (int index = 0; index < locals.Count; index++)
{
generator.Emit(OpCodes.Ldarg_1);
generator.Emit(OpCodes.Ldc_I4, outRegIndex++);
generator.Emit(OpCodes.Ldloc, locals[index]);
ConvertToFieldType(locals[index].LocalType);
generator.Emit(OpCodes.Stfld, GetStateFieldX(outRegIndex++));
MethodInfo info = typeof(IExecutionContext).GetMethod(nameof(IExecutionContext.SetX));
generator.Emit(OpCodes.Call, info);
}
// Zero out the remaining unused registers.
while (outRegIndex < SvcFuncMaxArguments)
{
generator.Emit(OpCodes.Ldarg_1);
generator.Emit(OpCodes.Ldc_I4, outRegIndex++);
generator.Emit(OpCodes.Ldc_I8, 0L);
generator.Emit(OpCodes.Stfld, GetStateFieldX(outRegIndex++));
MethodInfo info = typeof(IExecutionContext).GetMethod(nameof(IExecutionContext.SetX));
generator.Emit(OpCodes.Call, info);
}
generator.Emit(OpCodes.Ret);
return (Action<SvcHandler, CpuThreadState>)method.CreateDelegate(typeof(Action<SvcHandler, CpuThreadState>));
}
private static FieldInfo GetStateFieldX(int index)
{
switch (index)
{
case 0: return typeof(CpuThreadState).GetField(nameof(CpuThreadState.X0));
case 1: return typeof(CpuThreadState).GetField(nameof(CpuThreadState.X1));
case 2: return typeof(CpuThreadState).GetField(nameof(CpuThreadState.X2));
case 3: return typeof(CpuThreadState).GetField(nameof(CpuThreadState.X3));
case 4: return typeof(CpuThreadState).GetField(nameof(CpuThreadState.X4));
case 5: return typeof(CpuThreadState).GetField(nameof(CpuThreadState.X5));
case 6: return typeof(CpuThreadState).GetField(nameof(CpuThreadState.X6));
case 7: return typeof(CpuThreadState).GetField(nameof(CpuThreadState.X7));
}
throw new ArgumentOutOfRangeException(nameof(index));
return (Action<SvcHandler, IExecutionContext>)method.CreateDelegate(typeof(Action<SvcHandler, IExecutionContext>));
}
private static void CheckIfTypeIsSupported(Type type, string svcName)