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Add a new JIT compiler for CPU code (#693)

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* Start of the ARMeilleure project

* Refactoring around the old IRAdapter, now renamed to PreAllocator

* Optimize the LowestBitSet method

* Add CLZ support and fix CLS implementation

* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks

* Implement the ByteSwap IR instruction, and some refactoring on the assembler

* Implement the DivideUI IR instruction and fix 64-bits IDIV

* Correct constant operand type on CSINC

* Move division instructions implementation to InstEmitDiv

* Fix destination type for the ConditionalSelect IR instruction

* Implement UMULH and SMULH, with new IR instructions

* Fix some issues with shift instructions

* Fix constant types for BFM instructions

* Fix up new tests using the new V128 struct

* Update tests

* Move DIV tests to a separate file

* Add support for calls, and some instructions that depends on them

* Start adding support for SIMD & FP types, along with some of the related ARM instructions

* Fix some typos and the divide instruction with FP operands

* Fix wrong method call on Clz_V

* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes

* Implement SIMD logical instructions and more misc. fixes

* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations

* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes

* Implement SIMD shift instruction and fix Dup_V

* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table

* Fix check with tolerance on tester

* Implement FP & SIMD comparison instructions, and some fixes

* Update FCVT (Scalar) encoding on the table to support the Half-float variants

* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes

* Use old memory access methods, made a start on SIMD memory insts support, some fixes

* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes

* Fix arguments count with struct return values, other fixes

* More instructions

* Misc. fixes and integrate LDj3SNuD fixes

* Update tests

* Add a faster linear scan allocator, unwinding support on windows, and other changes

* Update Ryujinx.HLE

* Update Ryujinx.Graphics

* Fix V128 return pointer passing, RCX is clobbered

* Update Ryujinx.Tests

* Update ITimeZoneService

* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks

* Use generic GetFunctionPointerForDelegate method and other tweaks

* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics

* Remove some unused code on the assembler

* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler

* Add hardware capability detection

* Fix regression on Sha1h and revert Fcm** changes

* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator

* Fix silly mistake introduced on last commit on CpuId

* Generate inline stack probes when the stack allocation is too large

* Initial support for the System-V ABI

* Support multiple destination operands

* Fix SSE2 VectorInsert8 path, and other fixes

* Change placement of XMM callee save and restore code to match other compilers

* Rename Dest to Destination and Inst to Instruction

* Fix a regression related to calls and the V128 type

* Add an extra space on comments to match code style

* Some refactoring

* Fix vector insert FP32 SSE2 path

* Port over the ARM32 instructions

* Avoid memory protection races on JIT Cache

* Another fix on VectorInsert FP32 (thanks to LDj3SNuD

* Float operands don't need to use the same register when VEX is supported

* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks

* Some nits, small improvements on the pre allocator

* CpuThreadState is gone

* Allow changing CPU emulators with a config entry

* Add runtime identifiers on the ARMeilleure project

* Allow switching between CPUs through a config entry (pt. 2)

* Change win10-x64 to win-x64 on projects

* Update the Ryujinx project to use ARMeilleure

* Ensure that the selected register is valid on the hybrid allocator

* Allow exiting on returns to 0 (should fix test regression)

* Remove register assignments for most used variables on the hybrid allocator

* Do not use fixed registers as spill temp

* Add missing namespace and remove unneeded using

* Address PR feedback

* Fix types, etc

* Enable AssumeStrictAbiCompliance by default

* Ensure that Spill and Fill don't load or store any more than necessary
This commit is contained in:
gdkchan 2019-08-08 15:56:22 -03:00 • committed by emmauss
parent 1ba58e9942
commit a731ab3a2a
310 changed files with 37389 additions and 2086 deletions
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112
ChocolArm64/Instructions/SoftFloat.cs
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@ -82,7 +82,7 @@ namespace ChocolArm64.Instructions
{
public static float FPConvert(ushort valueBits, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat16_32.FPConvert: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat16_32.FPConvert: state.Fpcr = 0x{state.CFpcr:X8}");
double real = valueBits.FPUnpackCv(out FpType type, out bool sign, state);
@ -322,13 +322,13 @@ namespace ChocolArm64.Instructions
{
int enable = (int)exc + 8;
if ((state.Fpcr & (1 << enable)) != 0)
if ((state.CFpcr & (1 << enable)) != 0)
{
throw new NotImplementedException("Floating-point trap handling.");
}
else
{
state.Fpsr |= 1 << (int)exc;
state.CFpsr |= 1 << (int)exc;
}
}
}
@ -337,7 +337,7 @@ namespace ChocolArm64.Instructions
{
public static ushort FPConvert(float value, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32_16.FPConvert: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32_16.FPConvert: state.Fpcr = 0x{state.CFpcr:X8}");
double real = value.FPUnpackCv(out FpType type, out bool sign, out uint valueBits, state);
@ -609,13 +609,13 @@ namespace ChocolArm64.Instructions
{
int enable = (int)exc + 8;
if ((state.Fpcr & (1 << enable)) != 0)
if ((state.CFpcr & (1 << enable)) != 0)
{
throw new NotImplementedException("Floating-point trap handling.");
}
else
{
state.Fpsr |= 1 << (int)exc;
state.CFpsr |= 1 << (int)exc;
}
}
}
@ -624,7 +624,7 @@ namespace ChocolArm64.Instructions
{
public static float FPAdd(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPAdd: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPAdd: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2, state);
@ -672,7 +672,7 @@ namespace ChocolArm64.Instructions
public static int FPCompare(float value1, float value2, bool signalNaNs, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPCompare: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPCompare: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out _, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out _, state);
@ -709,7 +709,7 @@ namespace ChocolArm64.Instructions
public static float FPCompareEQ(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPCompareEQ: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPCompareEQ: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out _, out _, state);
value2 = value2.FPUnpack(out FpType type2, out _, out _, state);
@ -735,7 +735,7 @@ namespace ChocolArm64.Instructions
public static float FPCompareGE(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPCompareGE: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPCompareGE: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out _, out _, state);
value2 = value2.FPUnpack(out FpType type2, out _, out _, state);
@ -758,7 +758,7 @@ namespace ChocolArm64.Instructions
public static float FPCompareGT(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPCompareGT: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPCompareGT: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out _, out _, state);
value2 = value2.FPUnpack(out FpType type2, out _, out _, state);
@ -782,7 +782,7 @@ namespace ChocolArm64.Instructions
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public static float FPCompareLE(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPCompareLE: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPCompareLE: state.Fpcr = 0x{state.CFpcr:X8}");
return FPCompareGE(value2, value1, state);
}
@ -790,14 +790,14 @@ namespace ChocolArm64.Instructions
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public static float FPCompareLT(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPCompareLT: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPCompareLT: state.Fpcr = 0x{state.CFpcr:X8}");
return FPCompareGT(value2, value1, state);
}
public static float FPDiv(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPDiv: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPDiv: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2, state);
@ -846,7 +846,7 @@ namespace ChocolArm64.Instructions
public static float FPMax(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPMax: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPMax: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2, state);
@ -899,7 +899,7 @@ namespace ChocolArm64.Instructions
public static float FPMaxNum(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPMaxNum: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPMaxNum: state.Fpcr = 0x{state.CFpcr:X8}");
value1.FPUnpack(out FpType type1, out _, out _, state);
value2.FPUnpack(out FpType type2, out _, out _, state);
@ -918,7 +918,7 @@ namespace ChocolArm64.Instructions
public static float FPMin(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPMin: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPMin: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2, state);
@ -971,7 +971,7 @@ namespace ChocolArm64.Instructions
public static float FPMinNum(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPMinNum: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPMinNum: state.Fpcr = 0x{state.CFpcr:X8}");
value1.FPUnpack(out FpType type1, out _, out _, state);
value2.FPUnpack(out FpType type2, out _, out _, state);
@ -990,7 +990,7 @@ namespace ChocolArm64.Instructions
public static float FPMul(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPMul: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPMul: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2, state);
@ -1038,7 +1038,7 @@ namespace ChocolArm64.Instructions
float value2,
CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPMulAdd: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPMulAdd: state.Fpcr = 0x{state.CFpcr:X8}");
valueA = valueA.FPUnpack(out FpType typeA, out bool signA, out uint addend, state);
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1, state);
@ -1108,7 +1108,7 @@ namespace ChocolArm64.Instructions
float value2,
CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPMulSub: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPMulSub: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPNeg();
@ -1117,7 +1117,7 @@ namespace ChocolArm64.Instructions
public static float FPMulX(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPMulX: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPMulX: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2, state);
@ -1159,7 +1159,7 @@ namespace ChocolArm64.Instructions
public static float FPRecipEstimate(float value, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPRecipEstimate: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPRecipEstimate: state.Fpcr = 0x{state.CFpcr:X8}");
value.FPUnpack(out FpType type, out bool sign, out uint op, state);
@ -1248,7 +1248,7 @@ namespace ChocolArm64.Instructions
public static float FPRecipStepFused(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPRecipStepFused: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPRecipStepFused: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPNeg();
@ -1291,7 +1291,7 @@ namespace ChocolArm64.Instructions
public static float FPRecpX(float value, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPRecpX: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPRecpX: state.Fpcr = 0x{state.CFpcr:X8}");
value.FPUnpack(out FpType type, out bool sign, out uint op, state);
@ -1315,7 +1315,7 @@ namespace ChocolArm64.Instructions
public static float FPRSqrtEstimate(float value, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPRSqrtEstimate: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPRSqrtEstimate: state.Fpcr = 0x{state.CFpcr:X8}");
value.FPUnpack(out FpType type, out bool sign, out uint op, state);
@ -1380,7 +1380,7 @@ namespace ChocolArm64.Instructions
public static float FPRSqrtStepFused(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPRSqrtStepFused: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPRSqrtStepFused: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPNeg();
@ -1423,7 +1423,7 @@ namespace ChocolArm64.Instructions
public static float FPSqrt(float value, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPSqrt: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPSqrt: state.Fpcr = 0x{state.CFpcr:X8}");
value = value.FPUnpack(out FpType type, out bool sign, out uint op, state);
@ -1464,7 +1464,7 @@ namespace ChocolArm64.Instructions
public static float FPSub(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPSub: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPSub: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2, state);
@ -1693,13 +1693,13 @@ namespace ChocolArm64.Instructions
{
int enable = (int)exc + 8;
if ((state.Fpcr & (1 << enable)) != 0)
if ((state.CFpcr & (1 << enable)) != 0)
{
throw new NotImplementedException("Floating-point trap handling.");
}
else
{
state.Fpsr |= 1 << (int)exc;
state.CFpsr |= 1 << (int)exc;
}
}
}
@ -1708,7 +1708,7 @@ namespace ChocolArm64.Instructions
{
public static double FPAdd(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPAdd: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPAdd: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2, state);
@ -1756,7 +1756,7 @@ namespace ChocolArm64.Instructions
public static int FPCompare(double value1, double value2, bool signalNaNs, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPCompare: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPCompare: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out _, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out _, state);
@ -1793,7 +1793,7 @@ namespace ChocolArm64.Instructions
public static double FPCompareEQ(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPCompareEQ: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPCompareEQ: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out _, out _, state);
value2 = value2.FPUnpack(out FpType type2, out _, out _, state);
@ -1819,7 +1819,7 @@ namespace ChocolArm64.Instructions
public static double FPCompareGE(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPCompareGE: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPCompareGE: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out _, out _, state);
value2 = value2.FPUnpack(out FpType type2, out _, out _, state);
@ -1842,7 +1842,7 @@ namespace ChocolArm64.Instructions
public static double FPCompareGT(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPCompareGT: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPCompareGT: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out _, out _, state);
value2 = value2.FPUnpack(out FpType type2, out _, out _, state);
@ -1866,7 +1866,7 @@ namespace ChocolArm64.Instructions
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public static double FPCompareLE(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPCompareLE: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPCompareLE: state.Fpcr = 0x{state.CFpcr:X8}");
return FPCompareGE(value2, value1, state);
}
@ -1874,14 +1874,14 @@ namespace ChocolArm64.Instructions
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public static double FPCompareLT(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPCompareLT: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPCompareLT: state.Fpcr = 0x{state.CFpcr:X8}");
return FPCompareGT(value2, value1, state);
}
public static double FPDiv(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPDiv: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPDiv: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2, state);
@ -1930,7 +1930,7 @@ namespace ChocolArm64.Instructions
public static double FPMax(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPMax: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPMax: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2, state);
@ -1983,7 +1983,7 @@ namespace ChocolArm64.Instructions
public static double FPMaxNum(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPMaxNum: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPMaxNum: state.Fpcr = 0x{state.CFpcr:X8}");
value1.FPUnpack(out FpType type1, out _, out _, state);
value2.FPUnpack(out FpType type2, out _, out _, state);
@ -2002,7 +2002,7 @@ namespace ChocolArm64.Instructions
public static double FPMin(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPMin: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPMin: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2, state);
@ -2055,7 +2055,7 @@ namespace ChocolArm64.Instructions
public static double FPMinNum(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPMinNum: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPMinNum: state.Fpcr = 0x{state.CFpcr:X8}");
value1.FPUnpack(out FpType type1, out _, out _, state);
value2.FPUnpack(out FpType type2, out _, out _, state);
@ -2074,7 +2074,7 @@ namespace ChocolArm64.Instructions
public static double FPMul(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPMul: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPMul: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2, state);
@ -2122,7 +2122,7 @@ namespace ChocolArm64.Instructions
double value2,
CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPMulAdd: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPMulAdd: state.Fpcr = 0x{state.CFpcr:X8}");
valueA = valueA.FPUnpack(out FpType typeA, out bool signA, out ulong addend, state);
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1, state);
@ -2192,7 +2192,7 @@ namespace ChocolArm64.Instructions
double value2,
CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPMulSub: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPMulSub: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPNeg();
@ -2201,7 +2201,7 @@ namespace ChocolArm64.Instructions
public static double FPMulX(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPMulX: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPMulX: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2, state);
@ -2243,7 +2243,7 @@ namespace ChocolArm64.Instructions
public static double FPRecipEstimate(double value, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPRecipEstimate: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPRecipEstimate: state.Fpcr = 0x{state.CFpcr:X8}");
value.FPUnpack(out FpType type, out bool sign, out ulong op, state);
@ -2332,7 +2332,7 @@ namespace ChocolArm64.Instructions
public static double FPRecipStepFused(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPRecipStepFused: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPRecipStepFused: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPNeg();
@ -2375,7 +2375,7 @@ namespace ChocolArm64.Instructions
public static double FPRecpX(double value, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPRecpX: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPRecpX: state.Fpcr = 0x{state.CFpcr:X8}");
value.FPUnpack(out FpType type, out bool sign, out ulong op, state);
@ -2399,7 +2399,7 @@ namespace ChocolArm64.Instructions
public static double FPRSqrtEstimate(double value, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPRSqrtEstimate: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPRSqrtEstimate: state.Fpcr = 0x{state.CFpcr:X8}");
value.FPUnpack(out FpType type, out bool sign, out ulong op, state);
@ -2464,7 +2464,7 @@ namespace ChocolArm64.Instructions
public static double FPRSqrtStepFused(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPRSqrtStepFused: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPRSqrtStepFused: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPNeg();
@ -2507,7 +2507,7 @@ namespace ChocolArm64.Instructions
public static double FPSqrt(double value, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPSqrt: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPSqrt: state.Fpcr = 0x{state.CFpcr:X8}");
value = value.FPUnpack(out FpType type, out bool sign, out ulong op, state);
@ -2548,7 +2548,7 @@ namespace ChocolArm64.Instructions
public static double FPSub(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPSub: state.Fpcr = 0x{state.Fpcr:X8}");
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPSub: state.Fpcr = 0x{state.CFpcr:X8}");
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1, state);
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2, state);
@ -2777,13 +2777,13 @@ namespace ChocolArm64.Instructions
{
int enable = (int)exc + 8;
if ((state.Fpcr & (1 << enable)) != 0)
if ((state.CFpcr & (1 << enable)) != 0)
{
throw new NotImplementedException("Floating-point trap handling.");
}
else
{
state.Fpsr |= 1 << (int)exc;
state.CFpsr |= 1 << (int)exc;
}
}
}