Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
This commit is contained in:
gdkchan
emmauss
parent
1ba58e9942
commit
a731ab3a2a
310 changed files with 37389 additions and 2086 deletions
113
ARMeilleure/Decoders/DecoderHelper.cs
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113
ARMeilleure/Decoders/DecoderHelper.cs
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using ARMeilleure.Common;
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using System;
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namespace ARMeilleure.Decoders
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{
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static class DecoderHelper
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{
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public struct BitMask
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{
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public long WMask;
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public long TMask;
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public int Pos;
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public int Shift;
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public bool IsUndefined;
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public static BitMask Invalid => new BitMask { IsUndefined = true };
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}
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public static BitMask DecodeBitMask(int opCode, bool immediate)
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{
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int immS = (opCode >> 10) & 0x3f;
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int immR = (opCode >> 16) & 0x3f;
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int n = (opCode >> 22) & 1;
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int sf = (opCode >> 31) & 1;
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int length = BitUtils.HighestBitSet((~immS & 0x3f) | (n << 6));
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if (length < 1 || (sf == 0 && n != 0))
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{
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return BitMask.Invalid;
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}
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int size = 1 << length;
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int levels = size - 1;
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int s = immS & levels;
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int r = immR & levels;
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if (immediate && s == levels)
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{
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return BitMask.Invalid;
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}
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long wMask = BitUtils.FillWithOnes(s + 1);
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long tMask = BitUtils.FillWithOnes(((s - r) & levels) + 1);
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if (r > 0)
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{
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wMask = BitUtils.RotateRight(wMask, r, size);
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wMask &= BitUtils.FillWithOnes(size);
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}
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return new BitMask()
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{
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WMask = BitUtils.Replicate(wMask, size),
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TMask = BitUtils.Replicate(tMask, size),
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Pos = immS,
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Shift = immR
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};
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}
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public static long DecodeImm8Float(long imm, int size)
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{
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int e = 0, f = 0;
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switch (size)
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{
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case 0: e = 8; f = 23; break;
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case 1: e = 11; f = 52; break;
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default: throw new ArgumentOutOfRangeException(nameof(size));
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}
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long value = (imm & 0x3f) << f - 4;
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long eBit = (imm >> 6) & 1;
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long sBit = (imm >> 7) & 1;
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if (eBit != 0)
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{
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value |= (1L << e - 3) - 1 << f + 2;
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}
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value |= (eBit ^ 1) << f + e - 1;
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value |= sBit << f + e;
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return value;
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}
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public static long DecodeImm24_2(int opCode)
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{
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return ((long)opCode << 40) >> 38;
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}
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public static long DecodeImm26_2(int opCode)
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{
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return ((long)opCode << 38) >> 36;
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}
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public static long DecodeImmS19_2(int opCode)
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{
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return (((long)opCode << 40) >> 43) & ~3;
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}
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public static long DecodeImmS14_2(int opCode)
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{
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return (((long)opCode << 45) >> 48) & ~3;
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}
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}
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}
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