Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
This commit is contained in:
gdkchan
emmauss
parent
1ba58e9942
commit
a731ab3a2a
310 changed files with 37389 additions and 2086 deletions
190
ARMeilleure/CodeGen/X86/X86Instruction.cs
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190
ARMeilleure/CodeGen/X86/X86Instruction.cs
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namespace ARMeilleure.CodeGen.X86
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{
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enum X86Instruction
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{
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Add,
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Addpd,
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Addps,
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Addsd,
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Addss,
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And,
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Andnpd,
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Andnps,
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Bsr,
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Bswap,
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Call,
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Cmovcc,
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Cmp,
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Cmppd,
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Cmpps,
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Cmpsd,
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Cmpss,
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Cmpxchg16b,
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Comisd,
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Comiss,
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Cpuid,
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Cvtdq2pd,
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Cvtdq2ps,
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Cvtpd2dq,
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Cvtpd2ps,
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Cvtps2dq,
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Cvtps2pd,
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Cvtsd2si,
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Cvtsd2ss,
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Cvtsi2sd,
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Cvtsi2ss,
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Cvtss2sd,
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Div,
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Divpd,
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Divps,
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Divsd,
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Divss,
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Haddpd,
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Haddps,
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Idiv,
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Imul,
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Imul128,
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Insertps,
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Lea,
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Maxpd,
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Maxps,
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Maxsd,
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Maxss,
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Minpd,
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Minps,
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Minsd,
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Minss,
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Mov,
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Mov16,
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Mov8,
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Movd,
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Movdqu,
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Movhlps,
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Movlhps,
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Movq,
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Movsd,
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Movss,
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Movsx16,
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Movsx32,
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Movsx8,
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Movzx16,
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Movzx8,
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Mul128,
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Mulpd,
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Mulps,
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Mulsd,
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Mulss,
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Neg,
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Not,
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Or,
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Paddb,
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Paddd,
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Paddq,
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Paddw,
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Pand,
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Pandn,
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Pavgb,
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Pavgw,
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Pblendvb,
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Pcmpeqb,
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Pcmpeqd,
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Pcmpeqq,
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Pcmpeqw,
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Pcmpgtb,
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Pcmpgtd,
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Pcmpgtq,
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Pcmpgtw,
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Pextrb,
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Pextrd,
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Pextrq,
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Pextrw,
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Pinsrb,
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Pinsrd,
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Pinsrq,
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Pinsrw,
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Pmaxsb,
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Pmaxsd,
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Pmaxsw,
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Pmaxub,
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Pmaxud,
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Pmaxuw,
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Pminsb,
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Pminsd,
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Pminsw,
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Pminub,
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Pminud,
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Pminuw,
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Pmovsxbw,
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Pmovsxdq,
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Pmovsxwd,
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Pmovzxbw,
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Pmovzxdq,
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Pmovzxwd,
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Pmulld,
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Pmullw,
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Pop,
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Popcnt,
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Por,
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Pshufb,
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Pshufd,
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Pslld,
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Pslldq,
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Psllq,
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Psllw,
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Psrad,
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Psraw,
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Psrld,
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Psrlq,
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Psrldq,
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Psrlw,
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Psubb,
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Psubd,
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Psubq,
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Psubw,
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Punpckhbw,
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Punpckhdq,
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Punpckhqdq,
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Punpckhwd,
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Punpcklbw,
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Punpckldq,
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Punpcklqdq,
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Punpcklwd,
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Push,
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Pxor,
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Rcpps,
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Rcpss,
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Ror,
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Roundpd,
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Roundps,
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Roundsd,
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Roundss,
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Rsqrtps,
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Rsqrtss,
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Sar,
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Setcc,
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Shl,
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Shr,
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Shufpd,
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Shufps,
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Sqrtpd,
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Sqrtps,
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Sqrtsd,
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Sqrtss,
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Sub,
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Subpd,
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Subps,
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Subsd,
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Subss,
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Test,
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Unpckhpd,
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Unpckhps,
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Unpcklpd,
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Unpcklps,
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Vpblendvb,
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Xor,
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Xorpd,
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Xorps,
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Count
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}
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}
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