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Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104)

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* Update AOpCodeTable.cs

* Update AInstEmitSimdLogical.cs

* Update AInstEmitSimdArithmetic.cs

* Update ASoftFallback.cs

* Update AInstEmitAlu.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs
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LDj3SNuD 2018-04-26 04:20:22 +02:00 • committed by gdkchan
parent a38a72b062
commit a5ad1e9a06
9 changed files with 749 additions and 33 deletions
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5
Ryujinx.Tests/Cpu/Tester/Pseudocode.cs
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@ -253,6 +253,11 @@ namespace Ryujinx.Tests.Cpu.Tester
}
#endregion
#region "instrs/countop/"
// #CountOp
public enum CountOp {CountOp_CLZ, CountOp_CLS, CountOp_CNT};
#endregion
#region "instrs/extendreg/"
/* #impl-aarch64.DecodeRegExtend.1 */
public static ExtendType DecodeRegExtend(Bits op)