drashna/ryujinx
1
0
Fork 0
Code Activity Actions

Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484)

Browse source 
* Change naming convention for Ryujinx project

* Change naming convention for ChocolArm64 project

* Fix NaN

* Remove unneeded this. from Ryujinx project

* Adjust naming from new PRs

* Name changes based on feedback

* How did this get removed?

* Rebasing fix

* Change FP enum case

* Remove prefix from ChocolArm64 classes - Part 1

* Remove prefix from ChocolArm64 classes - Part 2

* Fix alignment from last commit's renaming

* Rename namespaces

* Rename stragglers

* Fix alignment

* Rename OpCode class

* Missed a few

* Adjust alignment
This commit is contained in:
Alex Barney 2018-10-30 19:43:02 -06:00 • committed by gdkchan
parent 5a87e58183
commit 9cb57fb4bb
314 changed files with 19456 additions and 19456 deletions
Download patch file Download diff file Expand all files Collapse all files

7
ChocolArm64/Instructions32/A32InstInterpretAlu.cs Normal file
View file

@ -0,0 +1,7 @@
namespace ChocolArm64.Instructions32
{
static partial class A32InstInterpret
{
}
}

70
ChocolArm64/Instructions32/A32InstInterpretFlow.cs Normal file
View file

@ -0,0 +1,70 @@
using ChocolArm64.Decoders;
using ChocolArm64.Decoders32;
using ChocolArm64.Memory;
using ChocolArm64.State;
using static ChocolArm64.Instructions32.A32InstInterpretHelper;
namespace ChocolArm64.Instructions32
{
static partial class A32InstInterpret
{
public static void B(CpuThreadState state, MemoryManager memory, OpCode64 opCode)
{
A32OpCodeBImmAl op = (A32OpCodeBImmAl)opCode;
if (IsConditionTrue(state, op.Cond))
{
BranchWritePc(state, GetPc(state) + (uint)op.Imm);
}
}
public static void Bl(CpuThreadState state, MemoryManager memory, OpCode64 opCode)
{
Blx(state, memory, opCode, false);
}
public static void Blx(CpuThreadState state, MemoryManager memory, OpCode64 opCode)
{
Blx(state, memory, opCode, true);
}
public static void Blx(CpuThreadState state, MemoryManager memory, OpCode64 opCode, bool x)
{
A32OpCodeBImmAl op = (A32OpCodeBImmAl)opCode;
if (IsConditionTrue(state, op.Cond))
{
uint pc = GetPc(state);
if (state.Thumb)
{
state.R14 = pc | 1;
}
else
{
state.R14 = pc - 4U;
}
if (x)
{
state.Thumb = !state.Thumb;
}
if (!state.Thumb)
{
pc &= ~3U;
}
BranchWritePc(state, pc + (uint)op.Imm);
}
}
private static void BranchWritePc(CpuThreadState state, uint pc)
{
state.R15 = state.Thumb
? pc & ~1U
: pc & ~3U;
}
}
}

65
ChocolArm64/Instructions32/A32InstInterpretHelper.cs Normal file
View file

@ -0,0 +1,65 @@
using ChocolArm64.Decoders;
using ChocolArm64.State;
using System;
namespace ChocolArm64.Instructions32
{
static class A32InstInterpretHelper
{
public static bool IsConditionTrue(CpuThreadState state, Cond cond)
{
switch (cond)
{
case Cond.Eq: return state.Zero;
case Cond.Ne: return !state.Zero;
case Cond.GeUn: return state.Carry;
case Cond.LtUn: return !state.Carry;
case Cond.Mi: return state.Negative;
case Cond.Pl: return !state.Negative;
case Cond.Vs: return state.Overflow;
case Cond.Vc: return !state.Overflow;
case Cond.GtUn: return state.Carry && !state.Zero;
case Cond.LeUn: return !state.Carry && state.Zero;
case Cond.Ge: return state.Negative == state.Overflow;
case Cond.Lt: return state.Negative != state.Overflow;
case Cond.Gt: return state.Negative == state.Overflow && !state.Zero;
case Cond.Le: return state.Negative != state.Overflow && state.Zero;
}
return true;
}
public unsafe static uint GetReg(CpuThreadState state, int reg)
{
if ((uint)reg > 15)
{
throw new ArgumentOutOfRangeException(nameof(reg));
}
fixed (uint* ptr = &state.R0)
{
return *(ptr + reg);
}
}
public unsafe static void SetReg(CpuThreadState state, int reg, uint value)
{
if ((uint)reg > 15)
{
throw new ArgumentOutOfRangeException(nameof(reg));
}
fixed (uint* ptr = &state.R0)
{
*(ptr + reg) = value;
}
}
public static uint GetPc(CpuThreadState state)
{
//Due to the old fetch-decode-execute pipeline of old ARM CPUs,
//the PC is 4 or 8 bytes (2 instructions) ahead of the current instruction.
return state.R15 + (state.Thumb ? 2U : 4U);
}
}
}