Implement inline memory load/store exclusive and ordered (#1413)
* Implement inline memory load/store exclusive * Fix missing REX prefix on 8-bits CMPXCHG * Increment PTC version due to bugfix * Remove redundant memory checks * Address PR feedback * Increment PPTC version
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57bb0abda3
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9878fc2d3c
19 changed files with 385 additions and 376 deletions
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@ -140,7 +140,7 @@ namespace ARMeilleure.Instructions
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false);
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Operand value = null;
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@ -157,6 +157,36 @@ namespace ARMeilleure.Instructions
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context.MarkLabel(lblEnd);
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}
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public static Operand EmitReadIntAligned(ArmEmitterContext context, Operand address, int size)
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{
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if ((uint)size > 4)
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{
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throw new ArgumentOutOfRangeException(nameof(size));
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}
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Operand isUnalignedAddr = EmitAddressCheck(context, address, size);
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Operand lblFastPath = Label();
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context.BranchIfFalse(lblFastPath, isUnalignedAddr);
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// The call is not expected to return (it should throw).
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context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ThrowInvalidMemoryAccess)), address);
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, null, write: false);
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return size switch
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{
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0 => context.Load8(physAddr),
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1 => context.Load16(physAddr),
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2 => context.Load(OperandType.I32, physAddr),
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3 => context.Load(OperandType.I64, physAddr),
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_ => context.Load(OperandType.V128, physAddr)
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};
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}
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private static void EmitReadVector(
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ArmEmitterContext context,
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Operand address,
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@ -181,7 +211,7 @@ namespace ARMeilleure.Instructions
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false);
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Operand value = null;
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@ -222,7 +252,7 @@ namespace ARMeilleure.Instructions
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: true);
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Operand value = GetInt(context, rt);
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@ -242,6 +272,45 @@ namespace ARMeilleure.Instructions
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context.MarkLabel(lblEnd);
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}
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public static void EmitWriteIntAligned(ArmEmitterContext context, Operand address, Operand value, int size)
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{
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if ((uint)size > 4)
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{
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throw new ArgumentOutOfRangeException(nameof(size));
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}
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Operand isUnalignedAddr = EmitAddressCheck(context, address, size);
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Operand lblFastPath = Label();
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context.BranchIfFalse(lblFastPath, isUnalignedAddr);
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// The call is not expected to return (it should throw).
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context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ThrowInvalidMemoryAccess)), address);
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, null, write: true);
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if (size < 3 && value.Type == OperandType.I64)
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{
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value = context.ConvertI64ToI32(value);
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}
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if (size == 0)
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{
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context.Store8(physAddr, value);
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}
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else if (size == 1)
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{
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context.Store16(physAddr, value);
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}
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else
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{
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context.Store(physAddr, value);
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}
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}
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private static void EmitWriteVector(
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ArmEmitterContext context,
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Operand address,
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@ -265,7 +334,7 @@ namespace ARMeilleure.Instructions
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: true);
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Operand value = GetVec(rt);
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@ -281,7 +350,7 @@ namespace ARMeilleure.Instructions
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context.MarkLabel(lblEnd);
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}
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private static Operand EmitAddressCheck(ArmEmitterContext context, Operand address, int size)
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public static Operand EmitAddressCheck(ArmEmitterContext context, Operand address, int size)
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{
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ulong addressCheckMask = ~((1UL << context.Memory.AddressSpaceBits) - 1);
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@ -290,7 +359,7 @@ namespace ARMeilleure.Instructions
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return context.BitwiseAnd(address, Const(address.Type, (long)addressCheckMask));
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}
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private static Operand EmitPtPointerLoad(ArmEmitterContext context, Operand address, Operand lblSlowPath)
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public static Operand EmitPtPointerLoad(ArmEmitterContext context, Operand address, Operand lblSlowPath, bool write)
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{
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int ptLevelBits = context.Memory.AddressSpaceBits - 12; // 12 = Number of page bits.
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int ptLevelSize = 1 << ptLevelBits;
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@ -302,6 +371,12 @@ namespace ARMeilleure.Instructions
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int bit = PageBits;
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// Load page table entry from the page table.
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// This was designed to support multi-level page tables of any size, however right
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// now we only use flat page tables (so there's only one level).
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// The page table entry contains the host address where the page is located.
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// Additionally, the higher 16-bits of the host address may contain extra information
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// used for write tracking, so this must be handled here aswell.
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do
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{
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Operand addrPart = context.ShiftRightUI(address, Const(bit));
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@ -326,7 +401,37 @@ namespace ARMeilleure.Instructions
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}
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while (bit < context.Memory.AddressSpaceBits);
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context.BranchIfTrue(lblSlowPath, context.ICompareLessOrEqual(pte, Const(0L)));
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if (lblSlowPath != null)
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{
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context.BranchIfTrue(lblSlowPath, context.ICompareLessOrEqual(pte, Const(0L)));
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}
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else
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{
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// When no label is provided to jump to a slow path if the address is invalid,
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// we do the validation ourselves, and throw if needed.
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if (write)
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{
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Operand lblNotWatched = Label();
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// Is the page currently being monitored for modifications? If so we need to call MarkRegionAsModified.
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context.BranchIfTrue(lblNotWatched, context.ICompareGreaterOrEqual(pte, Const(0L)));
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// Mark the region as modified. Size here doesn't matter as address is assumed to be size aligned here.
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context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.MarkRegionAsModified)), address, Const(1UL));
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context.MarkLabel(lblNotWatched);
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}
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Operand lblNonNull = Label();
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// Skip exception if the PTE address is non-null (not zero).
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context.BranchIfTrue(lblNonNull, pte);
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// The call is not expected to return (it should throw).
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context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ThrowInvalidMemoryAccess)), address);
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context.MarkLabel(lblNonNull);
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pte = context.BitwiseAnd(pte, Const(0xffffffffffffUL));
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}
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Operand pageOffset = context.BitwiseAnd(address, Const(address.Type, PageMask));
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