Add Smlal_Ve, Smlsl_Ve, Smull_Ve, Umlal_Ve, Umlsl_Ve, Umull_Ve Inst.; add Tests. Add Sse Opt. for Trn1/2_V and Uzp1/2_V Inst. Nits. (#566)
* Update OpCodeTable.cs * Update InstEmitSimdArithmetic.cs * Update InstEmitSimdHelper.cs * Update CpuTestSimdRegElem.cs * Update InstEmitSimdMove.cs * Update InstEmitSimdCvt.cs * Update SoftFallback.cs * Update InstEmitSimdHelper.cs * Update SoftFloat.cs * Update CryptoHelper.cs * Update InstEmitSimdArithmetic.cs * Update InstEmitSimdCmp.cs * Address PR feedback. * Address PR feedback.
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LDj3SNuD
gdkchan
parent
36b9ab0e48
commit
8f7fcede7f
10 changed files with 453 additions and 175 deletions
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@ -12,6 +12,34 @@ namespace ChocolArm64.Instructions
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{
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static partial class InstEmit
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{
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#region "Masks"
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private static readonly long[] _masksE0_TrnUzpXtn = new long[]
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{
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14L << 56 | 12L << 48 | 10L << 40 | 08L << 32 | 06L << 24 | 04L << 16 | 02L << 8 | 00L << 0,
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13L << 56 | 12L << 48 | 09L << 40 | 08L << 32 | 05L << 24 | 04L << 16 | 01L << 8 | 00L << 0,
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11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 03L << 24 | 02L << 16 | 01L << 8 | 00L << 0
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};
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private static readonly long[] _masksE1_TrnUzp = new long[]
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{
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15L << 56 | 13L << 48 | 11L << 40 | 09L << 32 | 07L << 24 | 05L << 16 | 03L << 8 | 01L << 0,
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15L << 56 | 14L << 48 | 11L << 40 | 10L << 32 | 07L << 24 | 06L << 16 | 03L << 8 | 02L << 0,
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15L << 56 | 14L << 48 | 13L << 40 | 12L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0
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};
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private static readonly long[] _masksE0_Uzp = new long[]
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{
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13L << 56 | 09L << 48 | 05L << 40 | 01L << 32 | 12L << 24 | 08L << 16 | 04L << 8 | 00L << 0,
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11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0
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};
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private static readonly long[] _masksE1_Uzp = new long[]
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{
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15L << 56 | 11L << 48 | 07L << 40 | 03L << 32 | 14L << 24 | 10L << 16 | 06L << 8 | 02L << 0,
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15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0
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};
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#endregion
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public static void Dup_Gp(ILEmitterCtx context)
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{
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OpCodeSimdIns64 op = (OpCodeSimdIns64)context.CurrOp;
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@ -379,15 +407,6 @@ namespace ChocolArm64.Instructions
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if (Optimizations.UseSsse3)
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{
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long[] masks = new long[]
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{
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14L << 56 | 12L << 48 | 10L << 40 | 08L << 32 | 06L << 24 | 04L << 16 | 02L << 8 | 00L << 0,
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13L << 56 | 12L << 48 | 09L << 40 | 08L << 32 | 05L << 24 | 04L << 16 | 01L << 8 | 00L << 0,
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11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 03L << 24 | 02L << 16 | 01L << 8 | 00L << 0
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};
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Type[] typesMov = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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Type[] typesSfl = new Type[] { typeof(Vector128<sbyte>), typeof(Vector128<sbyte>) };
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Type[] typesSve = new Type[] { typeof(long), typeof(long) };
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string nameMov = op.RegisterSize == RegisterSize.Simd128
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@ -397,18 +416,18 @@ namespace ChocolArm64.Instructions
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context.EmitLdvec(op.Rd);
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VectorHelper.EmitCall(context, nameof(VectorHelper.VectorSingleZero));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.MoveLowToHigh), typesMov));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.MoveLowToHigh)));
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EmitLdvecWithSignedCast(context, op.Rn, 0);
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EmitLdvecWithSignedCast(context, op.Rn, 0); // value
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context.EmitLdc_I8(masks[op.Size]);
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context.Emit(OpCodes.Dup);
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context.EmitLdc_I8(_masksE0_TrnUzpXtn[op.Size]); // mask
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context.Emit(OpCodes.Dup); // mask
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetVector128), typesSve));
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context.EmitCall(typeof(Ssse3).GetMethod(nameof(Ssse3.Shuffle), typesSfl));
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context.EmitCall(typeof(Ssse3).GetMethod(nameof(Ssse3.Shuffle), GetTypesSflUpk(0)));
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context.EmitCall(typeof(Sse).GetMethod(nameMov, typesMov));
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context.EmitCall(typeof(Sse).GetMethod(nameMov));
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context.EmitStvec(op.Rd);
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}
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@ -465,22 +484,61 @@ namespace ChocolArm64.Instructions
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{
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OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
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int words = op.GetBitsCount() >> 4;
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int pairs = words >> op.Size;
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for (int index = 0; index < pairs; index++)
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if (Optimizations.UseSsse3)
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{
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int idx = index << 1;
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Type[] typesSve = new Type[] { typeof(long), typeof(long) };
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EmitVectorExtractZx(context, op.Rn, idx + part, op.Size);
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EmitVectorExtractZx(context, op.Rm, idx + part, op.Size);
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string nameUpk = part == 0
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? nameof(Sse2.UnpackLow)
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: nameof(Sse2.UnpackHigh);
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EmitVectorInsertTmp(context, idx + 1, op.Size);
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EmitVectorInsertTmp(context, idx, op.Size);
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EmitLdvecWithSignedCast(context, op.Rn, op.Size); // value
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if (op.Size < 3)
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{
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context.EmitLdc_I8(_masksE1_TrnUzp [op.Size]); // maskE1
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context.EmitLdc_I8(_masksE0_TrnUzpXtn[op.Size]); // maskE0
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetVector128), typesSve));
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context.EmitCall(typeof(Ssse3).GetMethod(nameof(Ssse3.Shuffle), GetTypesSflUpk(0)));
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}
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EmitLdvecWithSignedCast(context, op.Rm, op.Size); // value
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if (op.Size < 3)
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{
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context.EmitLdc_I8(_masksE1_TrnUzp [op.Size]); // maskE1
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context.EmitLdc_I8(_masksE0_TrnUzpXtn[op.Size]); // maskE0
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetVector128), typesSve));
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context.EmitCall(typeof(Ssse3).GetMethod(nameof(Ssse3.Shuffle), GetTypesSflUpk(0)));
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}
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context.EmitCall(typeof(Sse2).GetMethod(nameUpk, GetTypesSflUpk(op.Size)));
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EmitStvecWithSignedCast(context, op.Rd, op.Size);
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}
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else
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{
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int words = op.GetBitsCount() >> 4;
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int pairs = words >> op.Size;
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context.EmitLdvectmp();
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context.EmitStvec(op.Rd);
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for (int index = 0; index < pairs; index++)
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{
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int idx = index << 1;
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EmitVectorExtractZx(context, op.Rn, idx + part, op.Size);
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EmitVectorExtractZx(context, op.Rm, idx + part, op.Size);
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EmitVectorInsertTmp(context, idx + 1, op.Size);
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EmitVectorInsertTmp(context, idx, op.Size);
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}
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context.EmitLdvectmp();
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context.EmitStvec(op.Rd);
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}
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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@ -492,26 +550,91 @@ namespace ChocolArm64.Instructions
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{
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OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
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int words = op.GetBitsCount() >> 4;
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int pairs = words >> op.Size;
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for (int index = 0; index < pairs; index++)
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if (Optimizations.UseSsse3)
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{
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int idx = index << 1;
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Type[] typesSve = new Type[] { typeof(long), typeof(long) };
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EmitVectorExtractZx(context, op.Rn, idx + part, op.Size);
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EmitVectorExtractZx(context, op.Rm, idx + part, op.Size);
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string nameUpk = part == 0
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? nameof(Sse2.UnpackLow)
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: nameof(Sse2.UnpackHigh);
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EmitVectorInsertTmp(context, pairs + index, op.Size);
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EmitVectorInsertTmp(context, index, op.Size);
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if (op.RegisterSize == RegisterSize.Simd128)
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{
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EmitLdvecWithSignedCast(context, op.Rn, op.Size); // value
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if (op.Size < 3)
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{
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context.EmitLdc_I8(_masksE1_TrnUzp [op.Size]); // maskE1
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context.EmitLdc_I8(_masksE0_TrnUzpXtn[op.Size]); // maskE0
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetVector128), typesSve));
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context.EmitCall(typeof(Ssse3).GetMethod(nameof(Ssse3.Shuffle), GetTypesSflUpk(0)));
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}
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EmitLdvecWithSignedCast(context, op.Rm, op.Size); // value
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if (op.Size < 3)
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{
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context.EmitLdc_I8(_masksE1_TrnUzp [op.Size]); // maskE1
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context.EmitLdc_I8(_masksE0_TrnUzpXtn[op.Size]); // maskE0
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetVector128), typesSve));
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context.EmitCall(typeof(Ssse3).GetMethod(nameof(Ssse3.Shuffle), GetTypesSflUpk(0)));
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}
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context.EmitCall(typeof(Sse2).GetMethod(nameUpk, GetTypesSflUpk(3)));
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EmitStvecWithSignedCast(context, op.Rd, op.Size);
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}
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else
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{
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EmitLdvecWithSignedCast(context, op.Rn, op.Size);
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EmitLdvecWithSignedCast(context, op.Rm, op.Size);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.UnpackLow), GetTypesSflUpk(op.Size))); // value
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if (op.Size < 2)
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{
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context.EmitLdc_I8(_masksE1_Uzp[op.Size]); // maskE1
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context.EmitLdc_I8(_masksE0_Uzp[op.Size]); // maskE0
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetVector128), typesSve));
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context.EmitCall(typeof(Ssse3).GetMethod(nameof(Ssse3.Shuffle), GetTypesSflUpk(0)));
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}
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VectorHelper.EmitCall(context, nameof(VectorHelper.VectorInt64Zero));
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context.EmitCall(typeof(Sse2).GetMethod(nameUpk, GetTypesSflUpk(3)));
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EmitStvecWithSignedCast(context, op.Rd, op.Size);
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}
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}
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context.EmitLdvectmp();
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context.EmitStvec(op.Rd);
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if (op.RegisterSize == RegisterSize.Simd64)
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else
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{
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EmitVectorZeroUpper(context, op.Rd);
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int words = op.GetBitsCount() >> 4;
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int pairs = words >> op.Size;
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for (int index = 0; index < pairs; index++)
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{
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int idx = index << 1;
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EmitVectorExtractZx(context, op.Rn, idx + part, op.Size);
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EmitVectorExtractZx(context, op.Rm, idx + part, op.Size);
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EmitVectorInsertTmp(context, pairs + index, op.Size);
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EmitVectorInsertTmp(context, index, op.Size);
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}
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context.EmitLdvectmp();
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context.EmitStvec(op.Rd);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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}
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@ -521,36 +644,26 @@ namespace ChocolArm64.Instructions
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if (Optimizations.UseSse2)
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{
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EmitLdvecWithUnsignedCast(context, op.Rn, op.Size);
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EmitLdvecWithUnsignedCast(context, op.Rm, op.Size);
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Type[] types = new Type[]
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{
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VectorUIntTypesPerSizeLog2[op.Size],
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VectorUIntTypesPerSizeLog2[op.Size]
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};
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string name = part == 0 || (part != 0 && op.RegisterSize == RegisterSize.Simd64)
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string nameUpk = part == 0
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? nameof(Sse2.UnpackLow)
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: nameof(Sse2.UnpackHigh);
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context.EmitCall(typeof(Sse2).GetMethod(name, types));
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EmitLdvecWithSignedCast(context, op.Rn, op.Size);
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EmitLdvecWithSignedCast(context, op.Rm, op.Size);
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if (op.RegisterSize == RegisterSize.Simd64 && part != 0)
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if (op.RegisterSize == RegisterSize.Simd128)
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{
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context.EmitLdc_I4(8);
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context.EmitCall(typeof(Sse2).GetMethod(nameUpk, GetTypesSflUpk(op.Size)));
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}
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else
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{
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.UnpackLow), GetTypesSflUpk(op.Size)));
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VectorHelper.EmitCall(context, nameof(VectorHelper.VectorInt64Zero));
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Type[] shTypes = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) };
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), shTypes));
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context.EmitCall(typeof(Sse2).GetMethod(nameUpk, GetTypesSflUpk(3)));
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}
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EmitStvecWithUnsignedCast(context, op.Rd, op.Size);
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if (op.RegisterSize == RegisterSize.Simd64 && part == 0)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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EmitStvecWithSignedCast(context, op.Rd, op.Size);
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}
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else
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{
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@ -579,5 +692,10 @@ namespace ChocolArm64.Instructions
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}
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}
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}
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private static Type[] GetTypesSflUpk(int size)
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{
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return new Type[] { VectorIntTypesPerSizeLog2[size], VectorIntTypesPerSizeLog2[size] };
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}
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}
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}
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