drashna/ryujinx
1
0
Fork 0
Code Activity Actions

Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449)

Browse source 
* Update AOpCodeTable.cs

* Update AInstEmitSimdMove.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdShift.cs

* Update ASoftFallback.cs

* Update ASoftFloat.cs

* Update AOpCodeSimdRegElemF.cs

* Update CpuTestSimdIns.cs

* Update CpuTestSimdRegElem.cs

* Create CpuTestSimdRegElemF.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Superseded Fmul_Se Test. Nit.

* Address PR feedback.

* Address PR feedback.

* Update AInstEmitSimdArithmetic.cs

* Update ASoftFallback.cs

* Update AInstEmitAlu.cs

* Update AInstEmitSimdShift.cs
This commit is contained in:
LDj3SNuD 2018-10-14 04:35:16 +02:00 • committed by gdkchan
parent ac1a379265
commit 894459fcd7
14 changed files with 938 additions and 228 deletions
Download patch file Download diff file Expand all files Collapse all files

91
ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
View file

@ -82,20 +82,6 @@ namespace ChocolArm64.Instruction
}
public static void Cls_V(AILEmitterCtx Context)
{
MethodInfo MthdInfo = typeof(ASoftFallback).GetMethod(nameof(ASoftFallback.CountLeadingSigns));
EmitCountLeadingBits(Context, () => Context.EmitCall(MthdInfo));
}
public static void Clz_V(AILEmitterCtx Context)
{
MethodInfo MthdInfo = typeof(ASoftFallback).GetMethod(nameof(ASoftFallback.CountLeadingZeros));
EmitCountLeadingBits(Context, () => Context.EmitCall(MthdInfo));
}
private static void EmitCountLeadingBits(AILEmitterCtx Context, Action Emit)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
@ -110,7 +96,44 @@ namespace ChocolArm64.Instruction
Context.EmitLdc_I4(ESize);
Emit();
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingSigns));
EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
}
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
public static void Clz_V(AILEmitterCtx Context)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
int Bytes = Op.GetBitsCount() >> 3;
int Elems = Bytes >> Op.Size;
int ESize = 8 << Op.Size;
for (int Index = 0; Index < Elems; Index++)
{
EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size);
if (Lzcnt.IsSupported && ESize == 32)
{
Context.Emit(OpCodes.Conv_U4);
Context.EmitCall(typeof(Lzcnt).GetMethod(nameof(Lzcnt.LeadingZeroCount), new Type[] { typeof(uint) }));
Context.Emit(OpCodes.Conv_U8);
}
else
{
Context.EmitLdc_I4(ESize);
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountLeadingZeros));
}
EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
}
@ -131,11 +154,14 @@ namespace ChocolArm64.Instruction
{
EmitVectorExtractZx(Context, Op.Rn, Index, 0);
Context.Emit(OpCodes.Conv_U4);
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountSetBits8));
Context.Emit(OpCodes.Conv_U8);
if (Popcnt.IsSupported)
{
Context.EmitCall(typeof(Popcnt).GetMethod(nameof(Popcnt.PopCount), new Type[] { typeof(ulong) }));
}
else
{
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountSetBits8));
}
EmitVectorInsert(Context, Op.Rd, Index, 0);
}
@ -440,6 +466,15 @@ namespace ChocolArm64.Instruction
});
}
public static void Fmls_Se(AILEmitterCtx Context)
{
EmitScalarTernaryOpByElemF(Context, () =>
{
Context.Emit(OpCodes.Mul);
Context.Emit(OpCodes.Sub);
});
}
public static void Fmls_V(AILEmitterCtx Context)
{
EmitVectorTernaryOpF(Context, () =>
@ -554,6 +589,14 @@ namespace ChocolArm64.Instruction
});
}
public static void Fmulx_Se(AILEmitterCtx Context)
{
EmitScalarBinaryOpByElemF(Context, () =>
{
EmitSoftFloatCall(Context, nameof(ASoftFloat_32.FPMulX));
});
}
public static void Fmulx_V(AILEmitterCtx Context)
{
EmitVectorBinaryOpF(Context, () =>
@ -562,6 +605,14 @@ namespace ChocolArm64.Instruction
});
}
public static void Fmulx_Ve(AILEmitterCtx Context)
{
EmitVectorBinaryOpByElemF(Context, () =>
{
EmitSoftFloatCall(Context, nameof(ASoftFloat_32.FPMulX));
});
}
public static void Fneg_S(AILEmitterCtx Context)
{
EmitScalarUnaryOpF(Context, () => Context.Emit(OpCodes.Neg));