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Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449)

Browse source 
* Update AOpCodeTable.cs

* Update AInstEmitSimdMove.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdShift.cs

* Update ASoftFallback.cs

* Update ASoftFloat.cs

* Update AOpCodeSimdRegElemF.cs

* Update CpuTestSimdIns.cs

* Update CpuTestSimdRegElem.cs

* Create CpuTestSimdRegElemF.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Superseded Fmul_Se Test. Nit.

* Address PR feedback.

* Address PR feedback.

* Update AInstEmitSimdArithmetic.cs

* Update ASoftFallback.cs

* Update AInstEmitAlu.cs

* Update AInstEmitSimdShift.cs
This commit is contained in:
LDj3SNuD 2018-10-14 04:35:16 +02:00 • committed by gdkchan
parent ac1a379265
commit 894459fcd7
14 changed files with 938 additions and 228 deletions
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27
ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs
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@ -8,15 +8,26 @@ namespace ChocolArm64.Decoder
public AOpCodeSimdRegElemF(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
if ((Size & 1) != 0)
switch ((OpCode >> 21) & 3) // sz:L
{
Index = (OpCode >> 11) & 1;
}
else
{
Index = (OpCode >> 21) & 1 |
(OpCode >> 10) & 2;
case 0: // H:0
Index = (OpCode >> 10) & 2; // 0, 2
break;
case 1: // H:1
Index = (OpCode >> 10) & 2;
Index++; // 1, 3
break;
case 2: // H
Index = (OpCode >> 11) & 1; // 0, 1
break;
default: Emitter = AInstEmit.Und; return;
}
}
}
}
}