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CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390)

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LDj3SNuD 2020-07-17 06:21:40 +02:00 • committed by GitHub
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commit 88619d71b8
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7 changed files with 103 additions and 55 deletions
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17
ARMeilleure/Decoders/OpCode32SimdRegWide.cs Normal file
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namespace ARMeilleure.Decoders
{
sealed class OpCode32SimdRegWide : OpCode32SimdReg
{
public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Q = false;
RegisterSize = RegisterSize.Simd64;
// Subclasses have their own handling of Vx to account for before checking.
if (GetType() == typeof(OpCode32SimdRegWide) && DecoderHelper.VectorArgumentsInvalid(true, Vd, Vn))
{
Instruction = InstDescriptor.Undefined;
}
}
}
}