Generate CIL for SCVTF (vector), add undefined encodings for some instructions
This commit is contained in:
gdkchan
parent
9e8d99f30d
commit
7d11a146c0
7 changed files with 340 additions and 285 deletions
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@ -104,8 +104,8 @@ namespace ChocolArm64.Instruction
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public static void Fadd_V(AILEmitterCtx Context) => EmitVectorBinaryFOp(Context, OpCodes.Add);
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public static void Fcvtzs_V(AILEmitterCtx Context) => EmitVectorFcvtS(Context);
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public static void Fcvtzu_V(AILEmitterCtx Context) => EmitVectorFcvtU(Context);
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public static void Fcvtzs_V(AILEmitterCtx Context) => EmitVectorFcvts(Context);
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public static void Fcvtzu_V(AILEmitterCtx Context) => EmitVectorFcvtu(Context);
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public static void Fmla_V(AILEmitterCtx Context)
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{
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@ -264,19 +264,7 @@ namespace ChocolArm64.Instruction
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Context.EmitStvec(Op.Rd);
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}
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public static void Scvtf_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdc_I4(Op.SizeF);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Scvtf_V64),
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nameof(ASoftFallback.Scvtf_V128));
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Context.EmitStvec(Op.Rd);
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}
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public static void Scvtf_V(AILEmitterCtx Context) => EmitVectorScvtf(Context);
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public static void Shl_V(AILEmitterCtx Context)
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{
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@ -346,7 +334,7 @@ namespace ChocolArm64.Instruction
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nameof(ASoftFallback.Tbl4_V128)); break;
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default: throw new InvalidOperationException();
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}
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}
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Context.EmitStvec(Op.Rd);
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}
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@ -434,33 +422,12 @@ namespace ChocolArm64.Instruction
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public static void Ushr_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdc_I4((8 << (Op.Size + 1)) - Op.Imm);
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Context.EmitLdc_I4(Op.Size);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Ushr64),
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nameof(ASoftFallback.Ushr128));
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Context.EmitStvec(Op.Rd);
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EmitVectorShr(Context, ShrFlags.None);
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}
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public static void Usra_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdc_I4((8 << (Op.Size + 1)) - Op.Imm);
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Context.EmitLdc_I4(Op.Size);
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ASoftFallback.EmitCall(Context,
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nameof(ASoftFallback.Usra64),
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nameof(ASoftFallback.Usra128));
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Context.EmitStvec(Op.Rd);
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EmitVectorShr(Context, ShrFlags.Accumulate);
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}
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public static void Uzp1_V(AILEmitterCtx Context)
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@ -651,11 +618,11 @@ namespace ChocolArm64.Instruction
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Context.EmitLdc_I4(0);
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Context.EmitLdc_I4(Op.Size);
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EmitVectorExtractZx(Context, Op.Rn, 0);
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EmitVectorExtractZx(Context, Op.Rn, 0, Op.Size);
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for (int Index = 1; Index < (Bytes >> Op.Size); Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, Index);
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EmitVectorExtractZx(Context, Op.Rn, Op.Size, Index);
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Context.Emit(OpCodes.Add);
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}
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@ -730,7 +697,7 @@ namespace ChocolArm64.Instruction
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int MaxShift = 8 << Op.Size;
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EmitVectorBinaryZx(Context, () =>
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Action Emit = () =>
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{
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AILLabel LblShl = new AILLabel();
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AILLabel LblZero = new AILLabel();
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@ -771,48 +738,83 @@ namespace ChocolArm64.Instruction
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Context.EmitLdc_I8(0);
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Context.MarkLabel(LblEnd);
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});
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};
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if (Signed)
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{
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EmitVectorBinarySx(Context, Emit);
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}
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else
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{
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EmitVectorBinaryZx(Context, Emit);
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}
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}
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private static void EmitVectorFcvtS(AILEmitterCtx Context)
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private enum ShrFlags
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{
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EmitVectorCvtOp(Context, CvtDir.Fcvt, true);
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None = 0,
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Signed = 1 << 0,
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Rounding = 1 << 1,
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Accumulate = 1 << 2
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}
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private static void EmitVectorFcvtU(AILEmitterCtx Context)
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private static void EmitVectorShr(AILEmitterCtx Context, ShrFlags Flags)
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{
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EmitVectorCvtOp(Context, CvtDir.Fcvt, false);
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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int Shift = (8 << (Op.Size + 1)) - Op.Imm;
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if (Flags.HasFlag(ShrFlags.Accumulate))
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{
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Action Emit = () =>
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{
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Context.EmitLdc_I4(Shift);
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Context.Emit(OpCodes.Shr_Un);
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Context.Emit(OpCodes.Add);
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};
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EmitVectorOp(Context, Emit, OperFlags.RdRn, Signed: false);
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}
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else
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{
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EmitVectorUnaryZx(Context, () =>
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{
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Context.EmitLdc_I4(Shift);
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Context.Emit(OpCodes.Shr_Un);
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});
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}
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}
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private static void EmitVectorCvtfS(AILEmitterCtx Context)
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private static void EmitVectorFcvts(AILEmitterCtx Context)
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{
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EmitVectorCvtOp(Context, CvtDir.Cvtf, true);
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EmitVectorFcvtOp(Context, Signed: true);
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}
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private static void EmitVectorCvtfU(AILEmitterCtx Context)
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private static void EmitVectorFcvtu(AILEmitterCtx Context)
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{
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EmitVectorCvtOp(Context, CvtDir.Cvtf, false);
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EmitVectorFcvtOp(Context, Signed: false);
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}
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private enum CvtDir
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private static void EmitVectorScvtf(AILEmitterCtx Context)
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{
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Fcvt,
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Cvtf
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EmitVectorCvtfOp(Context, Signed: true);
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}
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private static void EmitVectorCvtOp(AILEmitterCtx Context, CvtDir Dir, bool Signed)
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private static void EmitVectorUcvtf(AILEmitterCtx Context)
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{
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EmitVectorCvtfOp(Context, Signed: false);
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}
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private static void EmitVectorFcvtOp(AILEmitterCtx Context, bool Signed)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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int SizeI = SizeF + 2;
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int FBits = 0;
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if (Op is AOpCodeSimdShImm OpImm)
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{
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FBits = (8 << (Op.Size + 1)) - OpImm.Imm;
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}
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int FBits = GetFBits(Context);
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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@ -822,26 +824,17 @@ namespace ChocolArm64.Instruction
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Context.EmitLdc_I4(FBits);
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if (Dir == CvtDir.Fcvt)
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if (SizeF == 0)
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{
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//Float to Integer.
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if (SizeF == 0)
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{
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ASoftFallback.EmitCall(Context, Signed
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? nameof(ASoftFallback.SatSingleToInt32)
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: nameof(ASoftFallback.SatSingleToUInt32));
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}
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else if (SizeF == 1)
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{
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ASoftFallback.EmitCall(Context, Signed
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? nameof(ASoftFallback.SatDoubleToInt64)
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: nameof(ASoftFallback.SatDoubleToUInt64));
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}
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ASoftFallback.EmitCall(Context, Signed
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? nameof(ASoftFallback.SatSingleToInt32)
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: nameof(ASoftFallback.SatSingleToUInt32));
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}
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else if (Dir == CvtDir.Cvtf)
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else if (SizeF == 1)
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{
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//Integer to Float.
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//TODO.
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ASoftFallback.EmitCall(Context, Signed
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? nameof(ASoftFallback.SatDoubleToInt64)
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: nameof(ASoftFallback.SatDoubleToUInt64));
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}
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EmitVectorInsert(Context, Op.Rd, Index, SizeI);
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@ -853,6 +846,57 @@ namespace ChocolArm64.Instruction
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}
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}
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private static void EmitVectorCvtfOp(AILEmitterCtx Context, bool Signed)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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int SizeI = SizeF + 2;
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int FBits = GetFBits(Context);
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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for (int Index = 0; Index < (Bytes >> SizeI); Index++)
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{
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EmitVectorExtract(Context, Op.Rn, Index, SizeI, Signed);
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Context.EmitLdc_I4(FBits);
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if (SizeF == 0)
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{
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Context.Emit(OpCodes.Conv_I4);
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ASoftFallback.EmitCall(Context, Signed
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? nameof(ASoftFallback.Int32ToSingle)
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: nameof(ASoftFallback.UInt32ToSingle));
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}
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else if (SizeF == 1)
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{
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ASoftFallback.EmitCall(Context, Signed
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? nameof(ASoftFallback.Int64ToDouble)
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: nameof(ASoftFallback.UInt64ToDouble));
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}
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EmitVectorInsertF(Context, Op.Rd, Index, SizeF);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static int GetFBits(AILEmitterCtx Context)
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{
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if (Context.CurrOp is AOpCodeSimdShImm Op)
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{
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return (8 << (Op.Size + 1)) - Op.Imm;
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}
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return 0;
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}
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private static void EmitVectorBinaryFOp(AILEmitterCtx Context, OpCode ILOp)
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{
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EmitVectorBinaryFOp(Context, () => Context.Emit(ILOp));
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@ -899,36 +943,43 @@ namespace ChocolArm64.Instruction
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private static void EmitVectorUnarySx(AILEmitterCtx Context, Action Emit)
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{
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EmitVectorOp(Context, Emit, 1, true);
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EmitVectorOp(Context, Emit, OperFlags.Rn, true);
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}
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private static void EmitVectorBinarySx(AILEmitterCtx Context, Action Emit)
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{
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EmitVectorOp(Context, Emit, 2, true);
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EmitVectorOp(Context, Emit, OperFlags.RnRm, true);
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}
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private static void EmitVectorUnaryZx(AILEmitterCtx Context, Action Emit)
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{
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EmitVectorOp(Context, Emit, 1, false);
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EmitVectorOp(Context, Emit, OperFlags.Rn, false);
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}
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private static void EmitVectorBinaryZx(AILEmitterCtx Context, Action Emit)
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{
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EmitVectorOp(Context, Emit, 2, false);
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EmitVectorOp(Context, Emit, OperFlags.RnRm, false);
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}
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private static void EmitVectorTernaryZx(AILEmitterCtx Context, Action Emit)
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{
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EmitVectorOp(Context, Emit, 3, false);
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EmitVectorOp(Context, Emit, OperFlags.RdRnRm, false);
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}
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private static void EmitVectorOp(AILEmitterCtx Context, Action Emit, int Opers, bool Signed)
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[Flags]
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private enum OperFlags
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{
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if (Opers < 1 || Opers > 3)
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{
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throw new ArgumentOutOfRangeException(nameof(Opers));
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}
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Rd = 1 << 0,
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Rn = 1 << 1,
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Rm = 1 << 2,
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RnRm = Rn | Rm,
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RdRn = Rd | Rn,
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RdRnRm = Rd | Rn | Rm
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}
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private static void EmitVectorOp(AILEmitterCtx Context, Action Emit, OperFlags Opers, bool Signed)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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@ -939,19 +990,19 @@ namespace ChocolArm64.Instruction
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Context.EmitLdc_I4(Index);
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Context.EmitLdc_I4(Op.Size);
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if (Opers == 3)
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if (Opers.HasFlag(OperFlags.Rd))
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{
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EmitVectorExtract(Context, Op.Rd, Index, Signed);
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EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
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}
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if (Opers >= 1)
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if (Opers.HasFlag(OperFlags.Rn))
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{
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EmitVectorExtract(Context, Op.Rn, Index, Signed);
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
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}
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if (Opers >= 2)
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if (Opers.HasFlag(OperFlags.Rm))
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{
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EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, Index, Signed);
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EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, Index, Op.Size, Signed);
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}
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Emit();
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@ -999,7 +1050,7 @@ namespace ChocolArm64.Instruction
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Context.EmitLdc_I4(Index);
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Context.EmitLdc_I4(Op.Size);
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EmitVectorExtract(Context, Op.Rn, Index, Signed);
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
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Context.EmitLdc_I8(Imm);
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@ -1026,11 +1077,11 @@ namespace ChocolArm64.Instruction
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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{
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EmitVectorExtractSx(Context, Op.Rn, Index);
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EmitVectorExtractSx(Context, Op.Rn, Index, Op.Size);
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if (Op is AOpCodeSimdReg BinOp)
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{
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EmitVectorExtractSx(Context, BinOp.Rm, Index);
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EmitVectorExtractSx(Context, BinOp.Rm, Index, Op.Size);
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}
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else
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{
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@ -1078,29 +1129,39 @@ namespace ChocolArm64.Instruction
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}
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}
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private static void EmitVectorExtractSx(AILEmitterCtx Context, int Reg, int Index)
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private static void EmitVectorExtractSx(AILEmitterCtx Context, int Reg, int Index, int Size)
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{
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EmitVectorExtract(Context, Reg, Index, true);
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EmitVectorExtract(Context, Reg, Index, Size, true);
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}
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private static void EmitVectorExtractZx(AILEmitterCtx Context, int Reg, int Index)
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private static void EmitVectorExtractZx(AILEmitterCtx Context, int Reg, int Index, int Size)
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{
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EmitVectorExtract(Context, Reg, Index, false);
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EmitVectorExtract(Context, Reg, Index, Size, false);
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}
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private static void EmitVectorExtract(AILEmitterCtx Context, int Reg, int Index, bool Signed)
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private static void EmitVectorExtract(AILEmitterCtx Context, int Reg, int Index, int Size, bool Signed)
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{
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IAOpCodeSimd Op = (IAOpCodeSimd)Context.CurrOp;
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Context.EmitLdvec(Reg);
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Context.EmitLdc_I4(Index);
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Context.EmitLdc_I4(Op.Size);
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Context.EmitLdc_I4(Size);
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ASoftFallback.EmitCall(Context, Signed
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? nameof(ASoftFallback.ExtractSVec)
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: nameof(ASoftFallback.ExtractVec));
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}
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private static void EmitVectorZeroLower(AILEmitterCtx Context, int Rd)
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{
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EmitVectorInsert(Context, Rd, 0, 3, 0);
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}
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private static void EmitVectorZeroUpper(AILEmitterCtx Context, int Rd)
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{
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EmitVectorInsert(Context, Rd, 1, 3, 0);
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}
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private static void EmitVectorInsertF(AILEmitterCtx Context, int Reg, int Index, int Size)
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{
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Context.EmitLdvec(Reg);
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@ -1122,16 +1183,6 @@ namespace ChocolArm64.Instruction
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Context.EmitStvec(Reg);
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}
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private static void EmitVectorZeroLower(AILEmitterCtx Context, int Rd)
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{
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EmitVectorInsert(Context, Rd, 0, 3, 0);
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}
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private static void EmitVectorZeroUpper(AILEmitterCtx Context, int Rd)
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{
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EmitVectorInsert(Context, Rd, 1, 3, 0);
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}
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private static void EmitVectorInsert(AILEmitterCtx Context, int Reg, int Index, int Size)
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{
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Context.EmitLdvec(Reg);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue