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Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?)

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This commit is contained in:
gdkchan 2018-02-15 01:32:25 -03:00
parent 7c4346685c
commit 7c314eadcf
15 changed files with 674 additions and 1052 deletions
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18
Ryujinx/Cpu/Instruction/AInstEmitAluHelper.cs
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@ -21,13 +21,22 @@ namespace ChocolArm64.Instruction
public static void EmitAddsVCheck(AILEmitterCtx Context)
{
//V = (Rd ^ Rn) & ~(Rn ^ Rm) < 0
Context.Emit(OpCodes.Dup);
//V = (Rd ^ Rn) & (Rd ^ Rm) & ~(Rn ^ Rm) < 0
Context.EmitSttmp();
Context.EmitLdtmp();
Context.EmitLdtmp();
EmitDataLoadRn(Context);
Context.Emit(OpCodes.Xor);
Context.EmitLdtmp();
EmitDataLoadOper2(Context);
Context.Emit(OpCodes.Xor);
Context.Emit(OpCodes.And);
EmitDataLoadOpers(Context);
Context.Emit(OpCodes.Xor);
@ -47,7 +56,10 @@ namespace ChocolArm64.Instruction
EmitDataLoadOpers(Context);
Context.Emit(OpCodes.Clt_Un);
Context.Emit(OpCodes.Not);
Context.EmitLdc_I4(1);
Context.Emit(OpCodes.Xor);
Context.EmitStflg((int)APState.CBit);
}