CPU: A32: Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. (#1394)
* Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. * Update Ptc.cs
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4 changed files with 234 additions and 10 deletions
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@ -798,8 +798,9 @@ namespace ARMeilleure.Decoders
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SetA32("111100111x110000xxx0001100x0xxx0", InstName.Aese_V, InstEmit32.Aese_V, typeof(OpCode32Simd));
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SetA32("111100111x110000xxx0001111x0xxx0", InstName.Aesimc_V, InstEmit32.Aesimc_V, typeof(OpCode32Simd));
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SetA32("111100111x110000xxx0001110x0xxx0", InstName.Aesmc_V, InstEmit32.Aesmc_V, typeof(OpCode32Simd));
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SetA32("<<<<11101x110000xxxx10xx11x0xxxx", InstName.Vabs, InstEmit32.Vabs_S, typeof(OpCode32SimdS));
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SetA32("111100111x11xx01xxxx0x110xx0xxxx", InstName.Vabs, InstEmit32.Vabs_V, typeof(OpCode32Simd));
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SetA32("<<<<11101x110000xxxx101x11x0xxxx", InstName.Vabs, InstEmit32.Vabs_S, typeof(OpCode32SimdS));
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SetA32("111100111x11<<01xxxx00110xx0xxxx", InstName.Vabs, InstEmit32.Vabs_V, typeof(OpCode32SimdCmpZ));
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SetA32("111100111x111001xxxx01110xx0xxxx", InstName.Vabs, InstEmit32.Vabs_V, typeof(OpCode32SimdCmpZ));
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SetA32("111100100xxxxxxxxxxx1000xxx0xxxx", InstName.Vadd, InstEmit32.Vadd_I, typeof(OpCode32SimdReg));
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SetA32("<<<<11100x11xxxxxxxx101xx0x0xxxx", InstName.Vadd, InstEmit32.Vadd_S, typeof(OpCode32SimdRegS));
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SetA32("111100100x00xxxxxxxx1101xxx0xxxx", InstName.Vadd, InstEmit32.Vadd_V, typeof(OpCode32SimdReg));
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@ -897,7 +898,8 @@ namespace ARMeilleure.Decoders
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SetA32("1111001x1x000xxxxxxx10x00x11xxxx", InstName.Vmvn, InstEmit32.Vmvn_II, typeof(OpCode32SimdImm));
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SetA32("1111001x1x000xxxxxxx110x0x11xxxx", InstName.Vmvn, InstEmit32.Vmvn_II, typeof(OpCode32SimdImm));
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SetA32("<<<<11101x110001xxxx101x01x0xxxx", InstName.Vneg, InstEmit32.Vneg_S, typeof(OpCode32SimdS));
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SetA32("111100111x11xx01xxxx0x111xx0xxxx", InstName.Vneg, InstEmit32.Vneg_V, typeof(OpCode32Simd));
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SetA32("111100111x11<<01xxxx00111xx0xxxx", InstName.Vneg, InstEmit32.Vneg_V, typeof(OpCode32SimdCmpZ));
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SetA32("111100111x111001xxxx01111xx0xxxx", InstName.Vneg, InstEmit32.Vneg_V, typeof(OpCode32SimdCmpZ));
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SetA32("<<<<11100x01xxxxxxxx101xx1x0xxxx", InstName.Vnmla, InstEmit32.Vnmla_S, typeof(OpCode32SimdRegS));
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SetA32("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls, InstEmit32.Vnmls_S, typeof(OpCode32SimdRegS));
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SetA32("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul, InstEmit32.Vnmul_S, typeof(OpCode32SimdRegS));
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@ -33,7 +33,7 @@ namespace ARMeilleure.Instructions
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public static void Vabs_V(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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OpCode32SimdCmpZ op = (OpCode32SimdCmpZ)context.CurrOp;
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if (op.F)
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{
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@ -385,22 +385,22 @@ namespace ARMeilleure.Instructions
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public static void Vneg_V(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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OpCode32SimdCmpZ op = (OpCode32SimdCmpZ)context.CurrOp;
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if (op.F)
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{
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if (Optimizations.UseSse2)
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if (Optimizations.FastFP && Optimizations.UseSse2)
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{
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EmitVectorUnaryOpSimd32(context, (m) =>
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{
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if ((op.Size & 1) == 0)
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{
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Operand mask = X86GetScalar(context, -0f);
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Operand mask = X86GetAllElements(context, -0f);
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return context.AddIntrinsic(Intrinsic.X86Xorps, mask, m);
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}
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else
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{
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Operand mask = X86GetScalar(context, -0d);
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Operand mask = X86GetAllElements(context, -0d);
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return context.AddIntrinsic(Intrinsic.X86Xorpd, mask, m);
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}
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});
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@ -19,8 +19,8 @@ namespace ARMeilleure.Translation.PTC
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public static class Ptc
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{
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private const string HeaderMagic = "PTChd";
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private const int InternalVersion = 11; //! To be incremented manually for each change to the ARMeilleure project.
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private const int InternalVersion = 12; //! To be incremented manually for each change to the ARMeilleure project.
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private const string BaseDir = "Ryujinx";
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