drashna/ryujinx
1
0
Fork 0
Code Activity Actions

Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes (fast paths). (#1630)

Browse source 
* Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes (fast paths).

* Ptc.InternalVersion = 1630

* Nits.

* Address comments.

* Update Ptc.cs

* Address comment.
This commit is contained in:
LDj3SNuD 2020-12-07 10:37:07 +01:00 • committed by GitHub
parent 668720b088
commit 567ea726e1
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
14 changed files with 221 additions and 27 deletions
Download patch file Download diff file Expand all files Collapse all files

34
ARMeilleure/CodeGen/X86/CodeGenerator.cs
View file

@ -250,6 +250,40 @@ namespace ARMeilleure.CodeGen.X86
break;
}
case IntrinsicType.Mxcsr:
{
Operand offset = operation.GetSource(0);
Operand bits = operation.GetSource(1);
Debug.Assert(offset.Kind == OperandKind.Constant && bits.Kind == OperandKind.Constant);
Debug.Assert(offset.Type == OperandType.I32 && bits.Type == OperandType.I32);
int offs = offset.AsInt32() + context.CallArgsRegionSize;
Operand rsp = Register(X86Register.Rsp);
MemoryOperand memOp = MemoryOp(OperandType.I32, rsp, null, Multiplier.x1, offs);
Debug.Assert(HardwareCapabilities.SupportsSse || HardwareCapabilities.SupportsVexEncoding);
context.Assembler.Stmxcsr(memOp);
if (intrinOp.Intrinsic == Intrinsic.X86Mxcsrmb)
{
context.Assembler.Or(memOp, bits, OperandType.I32);
}
else /* if (intrinOp.Intrinsic == Intrinsic.X86Mxcsrub) */
{
Operand notBits = Const(~bits.AsInt32());
context.Assembler.And(memOp, notBits, OperandType.I32);
}
context.Assembler.Ldmxcsr(memOp);
break;
}
case IntrinsicType.PopCount:
{
Operand dest = operation.Destination;