drashna/ryujinx
1
0
Fork 0
Code Activity Actions

Add FMAXP and FMINP (Vector) instructions on the CPU (#412)

Browse source 
* Add FMAXP and FMINP (Vector) instructions on the CPU

* Address PR feedback
This commit is contained in:
gdkchan 2018-09-22 17:26:18 -03:00 • committed by GitHub
parent a76660eac5
commit 54ed9096bd
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
3 changed files with 183 additions and 158 deletions
Download patch file Download diff file Expand all files Collapse all files

36
ChocolArm64/Instruction/AInstEmitSimdHelper.cs
View file

@ -813,6 +813,42 @@ namespace ChocolArm64.Instruction
}
}
public static void EmitVectorPairwiseOpF(AILEmitterCtx Context, Action Emit)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
int SizeF = Op.Size & 1;
int Words = Op.GetBitsCount() >> 4;
int Pairs = Words >> SizeF + 2;
for (int Index = 0; Index < Pairs; Index++)
{
int Idx = Index << 1;
EmitVectorExtractF(Context, Op.Rn, Idx, SizeF);
EmitVectorExtractF(Context, Op.Rn, Idx + 1, SizeF);
Emit();
EmitVectorExtractF(Context, Op.Rm, Idx, SizeF);
EmitVectorExtractF(Context, Op.Rm, Idx + 1, SizeF);
Emit();
EmitVectorInsertTmpF(Context, Pairs + Index, SizeF);
EmitVectorInsertTmpF(Context, Index, SizeF);
}
Context.EmitLdvectmp();
Context.EmitStvec(Op.Rd);
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
[Flags]
public enum SaturatingFlags
{