drashna/ryujinx
1
0
Fork 0
Code Activity Actions

Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390)

Browse source 
* Update AOpCodeTable.cs

* Update AInstEmitSimdCvt.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update CpuTestSimd.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Add QCFlagBit.

* Add QCFlagBit.
This commit is contained in:
LDj3SNuD 2018-09-01 16:52:51 +02:00 • committed by gdkchan
parent 326777ca4a
commit 42e4e02a64
7 changed files with 2208 additions and 286 deletions
Download patch file Download diff file Expand all files Collapse all files

678
Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
View file

File diff suppressed because it is too large Load diff