Add Cmeq_S, Cmge_S, Cmgt_S, Cmhi_S, Cmhs_S, Cmle_S, Cmlt_S (Reg, Zero) & Cmtst_S compare instructions. Add 22 compare tests (Scalar, Vector). Add Eor_V, Not_V tests. (#171)
* Add files via upload * Add files via upload * Delete CpuTestScalar.cs * Update CpuTestSimdArithmetic.cs
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LDj3SNuD
gdkchan
parent
35e695552e
commit
3bdd109f45
20 changed files with 2624 additions and 338 deletions
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@ -49,6 +49,32 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[TestCase(0x1E224820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000000000000ul)]
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[TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000000000000ul, 0x0000000000000000ul)]
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[TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000080000000ul, 0x0000000080000000ul)]
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[TestCase(0x1E224820u, 0x0000000080000000ul, 0x000000003DCCCCCDul, 0x000000003DCCCCCDul)]
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[TestCase(0x1E224820u, 0x000000003DCCCCCDul, 0x000000003C9623B1ul, 0x000000003DCCCCCDul)]
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[TestCase(0x1E224820u, 0x000000008BA98D27ul, 0x0000000000000076ul, 0x0000000000000076ul)]
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[TestCase(0x1E224820u, 0x00000000807FFFFFul, 0x000000007F7FFFFFul, 0x000000007F7FFFFFul)]
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[TestCase(0x1E224820u, 0x000000007F7FFFFFul, 0x00000000807FFFFFul, 0x000000007F7FFFFFul)]
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[TestCase(0x1E224820u, 0x000000007FC00000ul, 0x000000003F800000ul, 0x000000007FC00000ul)]
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[TestCase(0x1E224820u, 0x000000003F800000ul, 0x000000007FC00000ul, 0x000000007FC00000ul)]
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[TestCase(0x1E224820u, 0x000000007F800001ul, 0x000000007FC00042ul, 0x000000007FC00001ul, Ignore = "NaN test.")]
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[TestCase(0x1E224820u, 0x000000007FC00042ul, 0x000000007F800001ul, 0x000000007FC00001ul, Ignore = "NaN test.")]
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[TestCase(0x1E224820u, 0x000000007FC0000Aul, 0x000000007FC0000Bul, 0x000000007FC0000Aul, Ignore = "NaN test.")]
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[TestCase(0x1E624820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x0000000000000000ul)]
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[TestCase(0x1E624820u, 0x8000000000000000ul, 0x0000000000000000ul, 0x0000000000000000ul)]
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[TestCase(0x1E624820u, 0x8000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)]
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[TestCase(0x1E624820u, 0x8000000000000000ul, 0x3FF3333333333333ul, 0x3FF3333333333333ul)]
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public void Fmax_S(uint Opcode, ulong A, ulong B, ulong Result)
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{
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// FMAX S0, S1, S2
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AThreadState ThreadState = SingleOpcode(Opcode,
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V1: Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, A)),
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V2: Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, B)));
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Assert.AreEqual(Result, Sse41.Extract(Sse.StaticCast<float, ulong>(ThreadState.V0), 0));
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}
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[TestCase(0x80000000u, 0x80000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u)]
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[TestCase(0x00000000u, 0x00000000u, 0x80000000u, 0x80000000u, 0x00000000u, 0x00000000u)]
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[TestCase(0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u)]
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@ -75,6 +101,32 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[TestCase(0x1E225820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000080000000ul)]
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[TestCase(0x1E225820u, 0x0000000080000000ul, 0x0000000000000000ul, 0x0000000080000000ul)]
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[TestCase(0x1E225820u, 0x0000000080000000ul, 0x0000000080000000ul, 0x0000000080000000ul)]
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[TestCase(0x1E225820u, 0x0000000080000000ul, 0x000000003DCCCCCDul, 0x0000000080000000ul)]
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[TestCase(0x1E225820u, 0x000000003DCCCCCDul, 0x000000003C9623B1ul, 0x000000003C9623B1ul)]
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[TestCase(0x1E225820u, 0x000000008BA98D27ul, 0x0000000000000076ul, 0x000000008BA98D27ul)]
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[TestCase(0x1E225820u, 0x00000000807FFFFFul, 0x000000007F7FFFFFul, 0x00000000807FFFFFul)]
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[TestCase(0x1E225820u, 0x000000007F7FFFFFul, 0x00000000807FFFFFul, 0x00000000807FFFFFul)]
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[TestCase(0x1E225820u, 0x000000007FC00000ul, 0x000000003F800000ul, 0x000000007FC00000ul)]
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[TestCase(0x1E225820u, 0x000000003F800000ul, 0x000000007FC00000ul, 0x000000007FC00000ul)]
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[TestCase(0x1E225820u, 0x000000007F800001ul, 0x000000007FC00042ul, 0x000000007FC00001ul, Ignore = "NaN test.")]
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[TestCase(0x1E225820u, 0x000000007FC00042ul, 0x000000007F800001ul, 0x000000007FC00001ul, Ignore = "NaN test.")]
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[TestCase(0x1E225820u, 0x000000007FC0000Aul, 0x000000007FC0000Bul, 0x000000007FC0000Aul, Ignore = "NaN test.")]
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[TestCase(0x1E625820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)]
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[TestCase(0x1E625820u, 0x8000000000000000ul, 0x0000000000000000ul, 0x8000000000000000ul)]
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[TestCase(0x1E625820u, 0x8000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)]
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[TestCase(0x1E625820u, 0x8000000000000000ul, 0x3FF3333333333333ul, 0x8000000000000000ul)]
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public void Fmin_S(uint Opcode, ulong A, ulong B, ulong Result)
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{
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// FMIN S0, S1, S2
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AThreadState ThreadState = SingleOpcode(Opcode,
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V1: Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, A)),
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V2: Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, B)));
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Assert.AreEqual(Result, Sse41.Extract(Sse.StaticCast<float, ulong>(ThreadState.V0), 0));
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}
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[TestCase(0x80000000u, 0x80000000u, 0x00000000u, 0x00000000u, 0x80000000u, 0x80000000u)]
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[TestCase(0x00000000u, 0x00000000u, 0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u)]
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[TestCase(0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u)]
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@ -101,7 +153,7 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[Test, Description("fmul s6, s1, v0.s[2]")]
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[Test, Description("FMUL S6, S1, V0.S[2]")]
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public void Fmul_Se([Random(10)] float A, [Random(10)] float B)
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{
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AThreadState ThreadState = SingleOpcode(0x5F809826,
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@ -111,7 +163,15 @@ namespace Ryujinx.Tests.Cpu
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Assert.That(Sse41.Extract(ThreadState.V6, (byte)0), Is.EqualTo(A * B));
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}
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[Test, Description("frecpe v2.4s, v0.4s")]
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[Test, Description("FRECPE D0, D1")]
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public void Frecpe_S([Random(100)] double A)
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{
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AThreadState ThreadState = SingleOpcode(0x5EE1D820, V1: MakeVectorE0(A));
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Assert.That(VectorExtractDouble(ThreadState.V0, 0), Is.EqualTo(1 / A));
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}
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[Test, Description("FRECPE V2.4S, V0.4S")]
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public void Frecpe_V([Random(100)] float A)
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{
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AThreadState ThreadState = SingleOpcode(0x4EA1D802, V0: Sse.SetAllVector128(A));
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@ -122,15 +182,17 @@ namespace Ryujinx.Tests.Cpu
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Assert.That(Sse41.Extract(ThreadState.V2, (byte)3), Is.EqualTo(1 / A));
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}
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[Test, Description("frecpe d0, d1")]
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public void Frecpe_S([Random(100)] double A)
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[Test, Description("FRECPS D0, D1, D2")]
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public void Frecps_S([Random(10)] double A, [Random(10)] double B)
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{
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AThreadState ThreadState = SingleOpcode(0x5EE1D820, V1: MakeVectorE0(A));
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AThreadState ThreadState = SingleOpcode(0x5E62FC20,
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V1: MakeVectorE0(A),
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V2: MakeVectorE0(B));
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Assert.That(VectorExtractDouble(ThreadState.V0, 0), Is.EqualTo(1 / A));
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Assert.That(VectorExtractDouble(ThreadState.V0, 0), Is.EqualTo(2 - (A * B)));
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}
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[Test, Description("frecps v4.4s, v2.4s, v0.4s")]
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[Test, Description("FRECPS V4.4S, V2.4S, V0.4S")]
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public void Frecps_V([Random(10)] float A, [Random(10)] float B)
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{
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AThreadState ThreadState = SingleOpcode(0x4E20FC44,
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@ -143,16 +205,6 @@ namespace Ryujinx.Tests.Cpu
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Assert.That(Sse41.Extract(ThreadState.V4, (byte)3), Is.EqualTo(2 - (A * B)));
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}
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[Test, Description("frecps d0, d1, d2")]
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public void Frecps_S([Random(10)] double A, [Random(10)] double B)
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{
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AThreadState ThreadState = SingleOpcode(0x5E62FC20,
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V1: MakeVectorE0(A),
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V2: MakeVectorE0(B));
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Assert.That(VectorExtractDouble(ThreadState.V0, 0), Is.EqualTo(2 - (A * B)));
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}
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[TestCase(0x3FE66666u, false, 0x40000000u)]
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[TestCase(0x3F99999Au, false, 0x3F800000u)]
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[TestCase(0x404CCCCDu, false, 0x40400000u)]
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