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Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77)

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* Update AOpCodeTable.cs

* Update AInstEmitSimdMove.cs

* Update CpuTestSimdMove.cs

* Update AInstEmitSimdMove.cs

* Update CpuTestSimdMove.cs
This commit is contained in:
LDj3SNuD 2018-04-12 16:52:00 +02:00 • committed by gdkchan
parent 9227b0ea59
commit 262b5b8054
3 changed files with 116 additions and 5 deletions
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35
ChocolArm64/Instruction/AInstEmitSimdMove.cs
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@ -256,6 +256,16 @@ namespace ChocolArm64.Instruction
Context.EmitStvec(Op.Rd);
}
public static void Trn1_V(AILEmitterCtx Context)
{
EmitVectorTranspose(Context, Part: 0);
}
public static void Trn2_V(AILEmitterCtx Context)
{
EmitVectorTranspose(Context, Part: 1);
}
public static void Umov_S(AILEmitterCtx Context)
{
AOpCodeSimdIns Op = (AOpCodeSimdIns)Context.CurrOp;
@ -315,6 +325,29 @@ namespace ChocolArm64.Instruction
}
}
private static void EmitVectorTranspose(AILEmitterCtx Context, int Part)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
int Elems = Bytes >> Op.Size;
for (int Index = 0; Index < Elems; Index++)
{
int Elem = (Index & ~1) + Part;
EmitVectorExtractZx(Context, (Index & 1) == 0 ? Op.Rn : Op.Rm, Elem, Op.Size);
EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
}
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
private static void EmitVectorUnzip(AILEmitterCtx Context, int Part)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
@ -363,4 +396,4 @@ namespace ChocolArm64.Instruction
}
}
}
}
}