drashna/ryujinx
1
0
Fork 0
Code Activity Actions

Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. (#614)

Browse source 
* Update CountLeadingZeros().

* Remove obsolete Tests.

* Follow-up.

* Follow-up.

* Follow-up.

* Add Mla_V, Mls_V & Mul_V Tests.

* Update PackageReferences.

* Remove EmitLd/Stvectmp2().

* Remove Dup. Nits.

* Remove EmitLd/Stvectmp2() & Dup; nits.

* Remove Tmp stuff & Dup; rework Fcvtz() as Fcvtn().

* Remove Tmp stuff, EmitLd/Stvectmp2() & Dup. Nits.

* Add (R)shrn_V Sse opt.; add "Part" & "Shift" opt..

Remove Tmp stuff; remove Dup.
Nits.

* Add Mla/Mls/Mul_V Sse opt.. Add "Part" opt..

Remove EmitLd/Stvectmp2(), remove Dup.
Nits.

* Nits.

* Nits.

* Nit.

* Add "Part" opt.. Nit.

* Nit.

* Nit.

* Add Cmhi_V & Cmhs_V Sse opt..
This commit is contained in:
LDj3SNuD 2019-03-13 09:23:52 +01:00 • committed by jduncanator
parent a0aecd1ff8
commit 1bef70c068
14 changed files with 707 additions and 484 deletions
Download patch file Download diff file Expand all files Collapse all files

7
Ryujinx.Tests/Cpu/CpuTestSimdExt.cs
View file

@ -19,7 +19,8 @@ namespace Ryujinx.Tests.Cpu
}
#endregion
private const int RndCnt = 2;
private const int RndCnt = 2;
private const int RndCntIndex = 2;
[Test, Pairwise, Description("EXT <Vd>.8B, <Vn>.8B, <Vm>.8B, #<index>")]
public void Ext_V_8B([Values(0u)] uint rd,
@ -28,7 +29,7 @@ namespace Ryujinx.Tests.Cpu
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
[ValueSource("_8B_")] [Random(RndCnt)] ulong b,
[Range(0u, 7u)] uint index)
[Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index)
{
uint imm4 = index & 0x7u;
@ -52,7 +53,7 @@ namespace Ryujinx.Tests.Cpu
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong a,
[ValueSource("_8B_")] [Random(RndCnt)] ulong b,
[Range(0u, 15u)] uint index)
[Values(0u, 15u)] [Random(1u, 14u, RndCntIndex)] uint index)
{
uint imm4 = index & 0xFu;