Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. (#614)
* Update CountLeadingZeros(). * Remove obsolete Tests. * Follow-up. * Follow-up. * Follow-up. * Add Mla_V, Mls_V & Mul_V Tests. * Update PackageReferences. * Remove EmitLd/Stvectmp2(). * Remove Dup. Nits. * Remove EmitLd/Stvectmp2() & Dup; nits. * Remove Tmp stuff & Dup; rework Fcvtz() as Fcvtn(). * Remove Tmp stuff, EmitLd/Stvectmp2() & Dup. Nits. * Add (R)shrn_V Sse opt.; add "Part" & "Shift" opt.. Remove Tmp stuff; remove Dup. Nits. * Add Mla/Mls/Mul_V Sse opt.. Add "Part" opt.. Remove EmitLd/Stvectmp2(), remove Dup. Nits. * Nits. * Nits. * Nit. * Add "Part" opt.. Nit. * Nit. * Nit. * Add Cmhi_V & Cmhs_V Sse opt..
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14 changed files with 707 additions and 484 deletions
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@ -8,26 +8,6 @@ namespace Ryujinx.Tests.Cpu
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{
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public class CpuTestSimdArithmetic : CpuTest
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{
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[TestCase(0x00000000u, 0x7F800000u)]
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[TestCase(0x80000000u, 0xFF800000u)]
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[TestCase(0x00FFF000u, 0x7E000000u)]
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[TestCase(0x41200000u, 0x3DCC8000u)]
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[TestCase(0xC1200000u, 0xBDCC8000u)]
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[TestCase(0x001FFFFFu, 0x7F800000u)]
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[TestCase(0x007FF000u, 0x7E800000u)]
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public void Frecpe_S(uint a, uint result)
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{
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uint opcode = 0x5EA1D820; // FRECPE S0, S1
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Vector128<float> v1 = MakeVectorE0(a);
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CpuThreadState threadState = SingleOpcode(opcode, v1: v1);
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Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(result));
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CompareAgainstUnicorn();
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}
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[TestCase(0x3FE66666u, false, 0x40000000u)]
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[TestCase(0x3F99999Au, false, 0x3F800000u)]
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[TestCase(0x404CCCCDu, false, 0x40400000u)]
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@ -601,19 +581,5 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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}
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[TestCase(0x41200000u, 0x3EA18000u)]
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public void Frsqrte_S(uint a, uint result)
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{
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uint opcode = 0x7EA1D820; // FRSQRTE S0, S1
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Vector128<float> v1 = MakeVectorE0(a);
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CpuThreadState threadState = SingleOpcode(opcode, v1: v1);
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Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(result));
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CompareAgainstUnicorn();
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}
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}
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}
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