Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. (#614)
* Update CountLeadingZeros(). * Remove obsolete Tests. * Follow-up. * Follow-up. * Follow-up. * Add Mla_V, Mls_V & Mul_V Tests. * Update PackageReferences. * Remove EmitLd/Stvectmp2(). * Remove Dup. Nits. * Remove EmitLd/Stvectmp2() & Dup; nits. * Remove Tmp stuff & Dup; rework Fcvtz() as Fcvtn(). * Remove Tmp stuff, EmitLd/Stvectmp2() & Dup. Nits. * Add (R)shrn_V Sse opt.; add "Part" & "Shift" opt.. Remove Tmp stuff; remove Dup. Nits. * Add Mla/Mls/Mul_V Sse opt.. Add "Part" opt.. Remove EmitLd/Stvectmp2(), remove Dup. Nits. * Nits. * Nits. * Nit. * Add "Part" opt.. Nit. * Nit. * Nit. * Add Cmhi_V & Cmhs_V Sse opt..
This commit is contained in:
LDj3SNuD
jduncanator
parent
a0aecd1ff8
commit
1bef70c068
14 changed files with 707 additions and 484 deletions
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@ -1,4 +1,5 @@
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// https://github.com/intel/ARM_NEON_2_x86_SSE/blob/master/NEON_2_SSE.h
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// https://www.agner.org/optimize/#vectorclass @ vectori128.h
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using ChocolArm64.Decoders;
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using ChocolArm64.State;
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@ -184,8 +185,8 @@ namespace ChocolArm64.Instructions
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if (sizeF == 0)
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{
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Type[] typesSsv = new Type[] { typeof(float) };
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Type[] typesSubAndNot = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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Type[] typesSsv = new Type[] { typeof(float) };
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Type[] typesSubAnt = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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context.EmitLdc_R4(-0f);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.SetScalarVector128), typesSsv));
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@ -193,8 +194,8 @@ namespace ChocolArm64.Instructions
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context.EmitLdvec(op.Rn);
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context.EmitLdvec(op.Rm);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.SubtractScalar), typesSubAndNot));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.AndNot), typesSubAndNot));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.SubtractScalar), typesSubAnt));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.AndNot), typesSubAnt));
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context.EmitStvec(op.Rd);
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@ -202,8 +203,8 @@ namespace ChocolArm64.Instructions
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}
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else /* if (sizeF == 1) */
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{
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Type[] typesSsv = new Type[] { typeof(double) };
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Type[] typesSubAndNot = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
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Type[] typesSsv = new Type[] { typeof(double) };
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Type[] typesSubAnt = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
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context.EmitLdc_R8(-0d);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetScalarVector128), typesSsv));
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@ -211,8 +212,8 @@ namespace ChocolArm64.Instructions
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context.EmitLdvec(op.Rn);
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context.EmitLdvec(op.Rm);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SubtractScalar), typesSubAndNot));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesSubAndNot));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SubtractScalar), typesSubAnt));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesSubAnt));
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context.EmitStvec(op.Rd);
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@ -240,8 +241,8 @@ namespace ChocolArm64.Instructions
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if (sizeF == 0)
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{
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Type[] typesSav = new Type[] { typeof(float) };
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Type[] typesSubAndNot = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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Type[] typesSav = new Type[] { typeof(float) };
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Type[] typesSubAnt = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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context.EmitLdc_R4(-0f);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.SetAllVector128), typesSav));
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@ -249,8 +250,8 @@ namespace ChocolArm64.Instructions
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context.EmitLdvec(op.Rn);
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context.EmitLdvec(op.Rm);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Subtract), typesSubAndNot));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.AndNot), typesSubAndNot));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Subtract), typesSubAnt));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.AndNot), typesSubAnt));
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context.EmitStvec(op.Rd);
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@ -261,8 +262,8 @@ namespace ChocolArm64.Instructions
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}
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else /* if (sizeF == 1) */
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{
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Type[] typesSav = new Type[] { typeof(double) };
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Type[] typesSubAndNot = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
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Type[] typesSav = new Type[] { typeof(double) };
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Type[] typesSubAnt = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
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context.EmitLdc_R8(-0d);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
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@ -270,8 +271,8 @@ namespace ChocolArm64.Instructions
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context.EmitLdvec(op.Rn);
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context.EmitLdvec(op.Rm);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Subtract), typesSubAndNot));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesSubAndNot));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Subtract), typesSubAnt));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesSubAnt));
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context.EmitStvec(op.Rd);
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}
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@ -295,15 +296,15 @@ namespace ChocolArm64.Instructions
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if (op.Size == 0)
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{
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Type[] typesSsv = new Type[] { typeof(float) };
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Type[] typesAndNot = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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Type[] typesSsv = new Type[] { typeof(float) };
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Type[] typesAnt = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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context.EmitLdc_R4(-0f);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.SetScalarVector128), typesSsv));
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context.EmitLdvec(op.Rn);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.AndNot), typesAndNot));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.AndNot), typesAnt));
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context.EmitStvec(op.Rd);
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@ -311,15 +312,15 @@ namespace ChocolArm64.Instructions
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}
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else /* if (op.Size == 1) */
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{
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Type[] typesSsv = new Type[] { typeof(double) };
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Type[] typesAndNot = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
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Type[] typesSsv = new Type[] { typeof(double) };
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Type[] typesAnt = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
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context.EmitLdc_R8(-0d);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetScalarVector128), typesSsv));
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context.EmitLdvec(op.Rn);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesAndNot));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesAnt));
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context.EmitStvec(op.Rd);
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@ -345,15 +346,15 @@ namespace ChocolArm64.Instructions
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if (sizeF == 0)
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{
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Type[] typesSav = new Type[] { typeof(float) };
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Type[] typesAndNot = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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Type[] typesSav = new Type[] { typeof(float) };
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Type[] typesAnt = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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context.EmitLdc_R4(-0f);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.SetAllVector128), typesSav));
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context.EmitLdvec(op.Rn);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.AndNot), typesAndNot));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.AndNot), typesAnt));
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context.EmitStvec(op.Rd);
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@ -364,15 +365,15 @@ namespace ChocolArm64.Instructions
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}
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else /* if (sizeF == 1) */
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{
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Type[] typesSav = new Type[] { typeof(double) };
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Type[] typesAndNot = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
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Type[] typesSav = new Type[] { typeof(double) };
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Type[] typesAnt = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
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context.EmitLdc_R8(-0d);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
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context.EmitLdvec(op.Rn);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesAndNot));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesAnt));
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context.EmitStvec(op.Rd);
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}
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@ -429,7 +430,7 @@ namespace ChocolArm64.Instructions
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Type[] typesAddH = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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context.EmitLdvec(op.Rn);
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context.Emit(OpCodes.Dup);
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context.EmitLdvec(op.Rn);
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context.EmitCall(typeof(Sse3).GetMethod(nameof(Sse3.HorizontalAdd), typesAddH));
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@ -442,7 +443,7 @@ namespace ChocolArm64.Instructions
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Type[] typesAddH = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
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context.EmitLdvec(op.Rn);
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context.Emit(OpCodes.Dup);
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context.EmitLdvec(op.Rn);
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context.EmitCall(typeof(Sse3).GetMethod(nameof(Sse3.HorizontalAdd), typesAddH));
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@ -748,11 +749,13 @@ namespace ChocolArm64.Instructions
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context.EmitLdvec(op.Rd);
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context.EmitLdvec(op.Rn);
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context.EmitLdvec(op.Rm);
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context.EmitLdvec(op.Rm);
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context.Emit(OpCodes.Dup);
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context.EmitLdc_I4(op.Index | op.Index << 2 | op.Index << 4 | op.Index << 6);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Multiply), typesMulAdd));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Add), typesMulAdd));
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@ -770,11 +773,13 @@ namespace ChocolArm64.Instructions
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context.EmitLdvec(op.Rd);
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context.EmitLdvec(op.Rn);
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context.EmitLdvec(op.Rm);
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context.EmitLdvec(op.Rm);
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context.Emit(OpCodes.Dup);
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context.EmitLdc_I4(op.Index | op.Index << 1);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Multiply), typesMulAdd));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), typesMulAdd));
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@ -863,11 +868,13 @@ namespace ChocolArm64.Instructions
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context.EmitLdvec(op.Rd);
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context.EmitLdvec(op.Rn);
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context.EmitLdvec(op.Rm);
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context.EmitLdvec(op.Rm);
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context.Emit(OpCodes.Dup);
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context.EmitLdc_I4(op.Index | op.Index << 2 | op.Index << 4 | op.Index << 6);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Multiply), typesMulSub));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Subtract), typesMulSub));
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@ -885,11 +892,13 @@ namespace ChocolArm64.Instructions
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context.EmitLdvec(op.Rd);
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context.EmitLdvec(op.Rn);
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context.EmitLdvec(op.Rm);
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context.EmitLdvec(op.Rm);
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context.Emit(OpCodes.Dup);
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context.EmitLdc_I4(op.Index | op.Index << 1);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Multiply), typesMulSub));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Subtract), typesMulSub));
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@ -1000,11 +1009,13 @@ namespace ChocolArm64.Instructions
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Type[] typesMul = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
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context.EmitLdvec(op.Rn);
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context.EmitLdvec(op.Rm);
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context.EmitLdvec(op.Rm);
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context.Emit(OpCodes.Dup);
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context.EmitLdc_I4(op.Index | op.Index << 2 | op.Index << 4 | op.Index << 6);
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Multiply), typesMul));
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context.EmitStvec(op.Rd);
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@ -1020,11 +1031,13 @@ namespace ChocolArm64.Instructions
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Type[] typesMul = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
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context.EmitLdvec(op.Rn);
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context.EmitLdvec(op.Rm);
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context.EmitLdvec(op.Rm);
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context.Emit(OpCodes.Dup);
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context.EmitLdc_I4(op.Index | op.Index << 1);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Shuffle), typesSfl));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Multiply), typesMul));
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context.EmitStvec(op.Rd);
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@ -1772,11 +1785,18 @@ namespace ChocolArm64.Instructions
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public static void Mla_V(ILEmitterCtx context)
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{
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EmitVectorTernaryOpZx(context, () =>
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if (Optimizations.UseSse41)
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{
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context.Emit(OpCodes.Mul);
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context.Emit(OpCodes.Add);
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});
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EmitSse41Mul_AddSub(context, nameof(Sse2.Add));
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}
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else
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{
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EmitVectorTernaryOpZx(context, () =>
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{
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context.Emit(OpCodes.Mul);
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context.Emit(OpCodes.Add);
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});
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}
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}
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public static void Mla_Ve(ILEmitterCtx context)
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@ -1790,11 +1810,18 @@ namespace ChocolArm64.Instructions
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public static void Mls_V(ILEmitterCtx context)
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{
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EmitVectorTernaryOpZx(context, () =>
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if (Optimizations.UseSse41)
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{
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context.Emit(OpCodes.Mul);
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context.Emit(OpCodes.Sub);
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});
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EmitSse41Mul_AddSub(context, nameof(Sse2.Subtract));
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}
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else
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{
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EmitVectorTernaryOpZx(context, () =>
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{
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context.Emit(OpCodes.Mul);
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context.Emit(OpCodes.Sub);
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});
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}
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}
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public static void Mls_Ve(ILEmitterCtx context)
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@ -1808,7 +1835,14 @@ namespace ChocolArm64.Instructions
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public static void Mul_V(ILEmitterCtx context)
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{
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EmitVectorBinaryOpZx(context, () => context.Emit(OpCodes.Mul));
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if (Optimizations.UseSse41)
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{
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EmitSse41Mul_AddSub(context);
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}
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else
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{
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EmitVectorBinaryOpZx(context, () => context.Emit(OpCodes.Mul));
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}
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}
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public static void Mul_Ve(ILEmitterCtx context)
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@ -1923,19 +1957,23 @@ namespace ChocolArm64.Instructions
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nameof(Sse41.ConvertToVector128Int32),
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nameof(Sse41.ConvertToVector128Int64) };
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int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0;
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context.EmitLdvec(op.Rn);
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context.EmitLdc_I4(numBytes);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
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if (op.RegisterSize == RegisterSize.Simd128)
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{
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context.Emit(OpCodes.Ldc_I4_8);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
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}
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context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
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context.EmitLdvec(op.Rm);
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context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
|
||||
|
||||
|
|
@ -1969,13 +2007,14 @@ namespace ChocolArm64.Instructions
|
|||
nameof(Sse41.ConvertToVector128Int32),
|
||||
nameof(Sse41.ConvertToVector128Int64) };
|
||||
|
||||
int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0;
|
||||
|
||||
context.EmitLdvec(op.Rn);
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
|
||||
|
||||
|
|
@ -1999,25 +2038,19 @@ namespace ChocolArm64.Instructions
|
|||
Type[] typesAndXorAdd = new Type[] { VectorIntTypesPerSizeLog2[op.Size], VectorIntTypesPerSizeLog2[op.Size] };
|
||||
|
||||
context.EmitLdvec(op.Rn);
|
||||
|
||||
context.Emit(OpCodes.Dup);
|
||||
context.EmitStvectmp();
|
||||
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.Emit(OpCodes.Dup);
|
||||
context.EmitStvectmp2();
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.And), typesAndXorAdd));
|
||||
|
||||
context.EmitLdvectmp();
|
||||
context.EmitLdvectmp2();
|
||||
context.EmitLdvec(op.Rn);
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Xor), typesAndXorAdd));
|
||||
|
||||
context.EmitLdc_I4(1);
|
||||
context.Emit(OpCodes.Ldc_I4_1);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightArithmetic), typesSra));
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), typesAndXorAdd));
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), typesAndXorAdd));
|
||||
|
||||
context.EmitStvec(op.Rd);
|
||||
|
||||
|
|
@ -2185,20 +2218,24 @@ namespace ChocolArm64.Instructions
|
|||
? nameof(Sse41.ConvertToVector128Int16)
|
||||
: nameof(Sse41.ConvertToVector128Int32);
|
||||
|
||||
int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0;
|
||||
|
||||
context.EmitLdvec(op.Rd);
|
||||
context.EmitLdvec(op.Rn);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(nameCvt, typesCvt));
|
||||
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(nameCvt, typesCvt));
|
||||
|
||||
|
|
@ -2244,20 +2281,24 @@ namespace ChocolArm64.Instructions
|
|||
? nameof(Sse41.ConvertToVector128Int16)
|
||||
: nameof(Sse41.ConvertToVector128Int32);
|
||||
|
||||
int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0;
|
||||
|
||||
context.EmitLdvec(op.Rd);
|
||||
context.EmitLdvec(op.Rn);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(nameCvt, typesCvt));
|
||||
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(nameCvt, typesCvt));
|
||||
|
||||
|
|
@ -2441,19 +2482,23 @@ namespace ChocolArm64.Instructions
|
|||
nameof(Sse41.ConvertToVector128Int32),
|
||||
nameof(Sse41.ConvertToVector128Int64) };
|
||||
|
||||
int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0;
|
||||
|
||||
context.EmitLdvec(op.Rn);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
|
||||
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
|
||||
|
||||
|
|
@ -2482,13 +2527,14 @@ namespace ChocolArm64.Instructions
|
|||
nameof(Sse41.ConvertToVector128Int32),
|
||||
nameof(Sse41.ConvertToVector128Int64) };
|
||||
|
||||
int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0;
|
||||
|
||||
context.EmitLdvec(op.Rn);
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
|
||||
|
||||
|
|
@ -2594,19 +2640,23 @@ namespace ChocolArm64.Instructions
|
|||
nameof(Sse41.ConvertToVector128Int32),
|
||||
nameof(Sse41.ConvertToVector128Int64) };
|
||||
|
||||
int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0;
|
||||
|
||||
context.EmitLdvec(op.Rn);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
|
||||
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
|
||||
|
||||
|
|
@ -2659,13 +2709,14 @@ namespace ChocolArm64.Instructions
|
|||
nameof(Sse41.ConvertToVector128Int32),
|
||||
nameof(Sse41.ConvertToVector128Int64) };
|
||||
|
||||
int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0;
|
||||
|
||||
context.EmitLdvec(op.Rn);
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
|
||||
|
||||
|
|
@ -2689,25 +2740,19 @@ namespace ChocolArm64.Instructions
|
|||
Type[] typesAndXorAdd = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], VectorUIntTypesPerSizeLog2[op.Size] };
|
||||
|
||||
context.EmitLdvec(op.Rn);
|
||||
|
||||
context.Emit(OpCodes.Dup);
|
||||
context.EmitStvectmp();
|
||||
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.Emit(OpCodes.Dup);
|
||||
context.EmitStvectmp2();
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.And), typesAndXorAdd));
|
||||
|
||||
context.EmitLdvectmp();
|
||||
context.EmitLdvectmp2();
|
||||
context.EmitLdvec(op.Rn);
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Xor), typesAndXorAdd));
|
||||
|
||||
context.EmitLdc_I4(1);
|
||||
context.Emit(OpCodes.Ldc_I4_1);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical), typesSrl));
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), typesAndXorAdd));
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Add), typesAndXorAdd));
|
||||
|
||||
context.EmitStvec(op.Rd);
|
||||
|
||||
|
|
@ -2737,8 +2782,7 @@ namespace ChocolArm64.Instructions
|
|||
Type[] typesAvgSub = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], VectorUIntTypesPerSizeLog2[op.Size] };
|
||||
|
||||
context.EmitLdvec(op.Rn);
|
||||
context.Emit(OpCodes.Dup);
|
||||
|
||||
context.EmitLdvec(op.Rn);
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Average), typesAvgSub));
|
||||
|
|
@ -2862,20 +2906,24 @@ namespace ChocolArm64.Instructions
|
|||
? nameof(Sse41.ConvertToVector128Int16)
|
||||
: nameof(Sse41.ConvertToVector128Int32);
|
||||
|
||||
int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0;
|
||||
|
||||
context.EmitLdvec(op.Rd);
|
||||
context.EmitLdvec(op.Rn);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(nameCvt, typesCvt));
|
||||
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(nameCvt, typesCvt));
|
||||
|
||||
|
|
@ -2921,20 +2969,24 @@ namespace ChocolArm64.Instructions
|
|||
? nameof(Sse41.ConvertToVector128Int16)
|
||||
: nameof(Sse41.ConvertToVector128Int32);
|
||||
|
||||
int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0;
|
||||
|
||||
context.EmitLdvec(op.Rd);
|
||||
context.EmitLdvec(op.Rn);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(nameCvt, typesCvt));
|
||||
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(nameCvt, typesCvt));
|
||||
|
||||
|
|
@ -3063,19 +3115,23 @@ namespace ChocolArm64.Instructions
|
|||
nameof(Sse41.ConvertToVector128Int32),
|
||||
nameof(Sse41.ConvertToVector128Int64) };
|
||||
|
||||
int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0;
|
||||
|
||||
context.EmitLdvec(op.Rn);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
|
||||
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
|
||||
|
||||
|
|
@ -3104,13 +3160,14 @@ namespace ChocolArm64.Instructions
|
|||
nameof(Sse41.ConvertToVector128Int32),
|
||||
nameof(Sse41.ConvertToVector128Int64) };
|
||||
|
||||
int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0;
|
||||
|
||||
context.EmitLdvec(op.Rn);
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.EmitLdc_I4(numBytes);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
if (op.RegisterSize == RegisterSize.Simd128)
|
||||
{
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), typesSrl));
|
||||
}
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(namesCvt[op.Size], typesCvt));
|
||||
|
||||
|
|
@ -3253,5 +3310,77 @@ namespace ChocolArm64.Instructions
|
|||
EmitVectorZeroUpper(context, op.Rd);
|
||||
}
|
||||
}
|
||||
|
||||
private static void EmitSse41Mul_AddSub(ILEmitterCtx context, string nameAddSub = null)
|
||||
{
|
||||
OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
|
||||
|
||||
if (nameAddSub != null)
|
||||
{
|
||||
context.EmitLdvec(op.Rd);
|
||||
}
|
||||
|
||||
if (op.Size == 0)
|
||||
{
|
||||
Type[] typesBle = new Type[] { typeof(Vector128<sbyte>), typeof(Vector128<sbyte>), typeof(Vector128<sbyte>) };
|
||||
Type[] typesMul = new Type[] { typeof(Vector128<short>), typeof(Vector128<short>) };
|
||||
Type[] typesShs = new Type[] { typeof(Vector128<short>), typeof(byte) };
|
||||
Type[] typesSav = new Type[] { typeof(int) };
|
||||
|
||||
context.EmitLdvec(op.Rn);
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical), typesShs));
|
||||
|
||||
context.EmitLdvec(op.Rm);
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical), typesShs));
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.MultiplyLow), typesMul));
|
||||
|
||||
context.Emit(OpCodes.Ldc_I4_8);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftLeftLogical), typesShs));
|
||||
|
||||
context.EmitLdvec(op.Rn);
|
||||
context.EmitLdvec(op.Rm);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.MultiplyLow), typesMul));
|
||||
|
||||
context.EmitLdc_I4(0x00FF00FF);
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(nameof(Sse41.BlendVariable), typesBle));
|
||||
}
|
||||
else if (op.Size == 1)
|
||||
{
|
||||
Type[] typesMul = new Type[] { typeof(Vector128<short>), typeof(Vector128<short>) };
|
||||
|
||||
context.EmitLdvec(op.Rn);
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.MultiplyLow), typesMul));
|
||||
}
|
||||
else /* if (op.Size == 2) */
|
||||
{
|
||||
Type[] typesMul = new Type[] { typeof(Vector128<int>), typeof(Vector128<int>) };
|
||||
|
||||
context.EmitLdvec(op.Rn);
|
||||
context.EmitLdvec(op.Rm);
|
||||
|
||||
context.EmitCall(typeof(Sse41).GetMethod(nameof(Sse41.MultiplyLow), typesMul));
|
||||
}
|
||||
|
||||
if (nameAddSub != null)
|
||||
{
|
||||
Type[] typesAddSub = new Type[] { VectorIntTypesPerSizeLog2[op.Size], VectorIntTypesPerSizeLog2[op.Size] };
|
||||
|
||||
context.EmitCall(typeof(Sse2).GetMethod(nameAddSub, typesAddSub));
|
||||
}
|
||||
|
||||
context.EmitStvec(op.Rd);
|
||||
|
||||
if (op.RegisterSize == RegisterSize.Simd64)
|
||||
{
|
||||
EmitVectorZeroUpper(context, op.Rd);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue