Add the TamperMachine module for runtime mods and cheats (#1928)
* Add initial implementation of the Tamper Machine * Implement Atmosphere opcodes 0, 4 and 9 * Add missing TamperCompilationException class * Implement Atmosphere conditional and loop opcodes 1, 2 and 3 * Inplement input conditional opcode 8 * Add register store opcode A * Implement extended pause/resume opcodes FF0 and FF1 * Implement extended log opcode FFF * Implement extended register conditional opcode C0 * Refactor TamperProgram to an interface * Moved Atmosphere classes to a separate subdirectory * Fix OpProcCtrl class not setting process * Implement extended register save/restore opcodes C1, C2 and C3 * Refactor code emitters to separate classes * Supress memory access errors from the Tamper Machine * Add debug information to tamper register and memory writes * Add block stack check to Atmosphere Cheat compiler * Add handheld input support to Tamper Machine * Fix code styling * Fix build id and cheat case mismatch * Fix invalid immediate size selection * Print build ids of the title * Prevent Tamper Machine from change code regions * Remove Atmosphere namespace * Remove empty cheats from the list * Prevent code modification without disabling the tampering * Fix missing addressing mode in LoadRegisterWithMemory * Fix wrong addressing in RegisterConditional * Add name to the tamper machine thread * Fix code styling
This commit is contained in:
parent
a5d5ca0635
commit
0c1ea1212a
71 changed files with 2793 additions and 5 deletions
105
Ryujinx.HLE/HOS/Tamper/CodeEmitters/Arithmetic.cs
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105
Ryujinx.HLE/HOS/Tamper/CodeEmitters/Arithmetic.cs
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@ -0,0 +1,105 @@
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using Ryujinx.HLE.Exceptions;
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using Ryujinx.HLE.HOS.Tamper.Operations;
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using System;
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using System.Collections.Generic;
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namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
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{
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/// <summary>
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/// Code type 9 allows performing arithmetic on registers.
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/// </summary>
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class Arithmetic
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{
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private const int OperationWidthIndex = 1;
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private const int OperationTypeIndex = 2;
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private const int DestinationRegisterIndex = 3;
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private const int LeftHandSideRegisterIndex = 4;
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private const int UseImmediateAsRhsIndex = 5;
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private const int RightHandSideRegisterIndex = 6;
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private const int RightHandSideImmediateIndex = 8;
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private const int RightHandSideImmediate8 = 8;
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private const int RightHandSideImmediate16 = 16;
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private const byte Add = 0; // lhs + rhs
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private const byte Sub = 1; // lhs - rhs
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private const byte Mul = 2; // lhs * rhs
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private const byte Lsh = 3; // lhs << rhs
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private const byte Rsh = 4; // lhs >> rhs
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private const byte And = 5; // lhs & rhs
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private const byte Or = 6; // lhs | rhs
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private const byte Not = 7; // ~lhs (discards right-hand operand)
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private const byte Xor = 8; // lhs ^ rhs
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private const byte Mov = 9; // lhs (discards right-hand operand)
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public static void Emit(byte[] instruction, CompilationContext context)
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{
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// 9TCRS0s0
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// T: Width of arithmetic operation(1, 2, 4, or 8 bytes).
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// C: Arithmetic operation to apply, see below.
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// R: Register to store result in.
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// S: Register to use as left - hand operand.
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// s: Register to use as right - hand operand.
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// 9TCRS100 VVVVVVVV (VVVVVVVV)
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// T: Width of arithmetic operation(1, 2, 4, or 8 bytes).
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// C: Arithmetic operation to apply, see below.
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// R: Register to store result in.
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// S: Register to use as left - hand operand.
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// V: Value to use as right - hand operand.
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byte operationWidth = instruction[OperationWidthIndex];
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byte operation = instruction[OperationTypeIndex];
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Register destinationRegister = context.GetRegister(instruction[DestinationRegisterIndex]);
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Register leftHandSideRegister = context.GetRegister(instruction[LeftHandSideRegisterIndex]);
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byte rightHandSideIsImmediate = instruction[UseImmediateAsRhsIndex];
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IOperand rightHandSideOperand;
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switch (rightHandSideIsImmediate)
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{
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case 0:
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// Use a register as right-hand side.
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rightHandSideOperand = context.GetRegister(instruction[RightHandSideRegisterIndex]);
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break;
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case 1:
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// Use an immediate as right-hand side.
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int immediateSize = operationWidth <= 4 ? RightHandSideImmediate8 : RightHandSideImmediate16;
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ulong immediate = InstructionHelper.GetImmediate(instruction, RightHandSideImmediateIndex, immediateSize);
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rightHandSideOperand = new Value<ulong>(immediate);
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break;
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default:
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throw new TamperCompilationException($"Invalid right-hand side switch {rightHandSideIsImmediate} in Atmosphere cheat");
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}
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void Emit(Type operationType, IOperand rhs = null)
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{
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List<IOperand> operandList = new List<IOperand>();
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operandList.Add(destinationRegister);
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operandList.Add(leftHandSideRegister);
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if (rhs != null)
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{
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operandList.Add(rhs);
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}
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InstructionHelper.Emit(operationType, operationWidth, context, operandList.ToArray());
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}
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switch (operation)
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{
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case Add: Emit(typeof(OpAdd<>), rightHandSideOperand); break;
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case Sub: Emit(typeof(OpSub<>), rightHandSideOperand); break;
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case Mul: Emit(typeof(OpMul<>), rightHandSideOperand); break;
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case Lsh: Emit(typeof(OpLsh<>), rightHandSideOperand); break;
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case Rsh: Emit(typeof(OpRsh<>), rightHandSideOperand); break;
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case And: Emit(typeof(OpAnd<>), rightHandSideOperand); break;
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case Or: Emit(typeof(OpOr<> ), rightHandSideOperand); break;
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case Not: Emit(typeof(OpNot<>) ); break;
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case Xor: Emit(typeof(OpXor<>), rightHandSideOperand); break;
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case Mov: Emit(typeof(OpMov<>) ); break;
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default:
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throw new TamperCompilationException($"Invalid arithmetic operation {operation} in Atmosphere cheat");
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}
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}
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}
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}
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14
Ryujinx.HLE/HOS/Tamper/CodeEmitters/BeginConditionalBlock.cs
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14
Ryujinx.HLE/HOS/Tamper/CodeEmitters/BeginConditionalBlock.cs
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namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
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{
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/// <summary>
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/// Marks the begin of a conditional block (started by Code Type 1, Code Type 8 or Code Type C0).
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/// </summary>
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class BeginConditionalBlock
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{
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public static void Emit(byte[] instruction, CompilationContext context)
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{
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// Just start a new compilation block and parse the instruction itself at the end.
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context.BlockStack.Push(new OperationBlock(instruction));
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}
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}
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}
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87
Ryujinx.HLE/HOS/Tamper/CodeEmitters/DebugLog.cs
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87
Ryujinx.HLE/HOS/Tamper/CodeEmitters/DebugLog.cs
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@ -0,0 +1,87 @@
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using Ryujinx.HLE.Exceptions;
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using Ryujinx.HLE.HOS.Tamper.Operations;
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namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
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{
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/// <summary>
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/// Code type 0xFFF writes a debug log.
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/// </summary>
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class DebugLog
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{
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private const int OperationWidthIndex = 3;
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private const int LogIdIndex = 4;
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private const int OperandTypeIndex = 5;
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private const int RegisterOrMemoryRegionIndex = 6;
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private const int OffsetRegisterOrImmediateIndex = 7;
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private const int MemoryRegionWithOffsetImmediate = 0;
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private const int MemoryRegionWithOffsetRegister = 1;
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private const int AddressRegisterWithOffsetImmediate = 2;
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private const int AddressRegisterWithOffsetRegister = 3;
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private const int ValueRegister = 4;
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private const int OffsetImmediateSize = 9;
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public static void Emit(byte[] instruction, CompilationContext context)
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{
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// FFFTIX##
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// FFFTI0Ma aaaaaaaa
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// FFFTI1Mr
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// FFFTI2Ra aaaaaaaa
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// FFFTI3Rr
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// FFFTI4V0
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// T: Width of memory write (1, 2, 4, or 8 bytes).
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// I: Log id.
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// X: Operand Type, see below.
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// M: Memory Type (operand types 0 and 1).
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// R: Address Register (operand types 2 and 3).
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// a: Relative Address (operand types 0 and 2).
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// r: Offset Register (operand types 1 and 3).
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// V: Value Register (operand type 4).
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byte operationWidth = instruction[OperationWidthIndex];
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byte logId = instruction[LogIdIndex];
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byte operandType = instruction[OperandTypeIndex];
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byte registerOrMemoryRegion = instruction[RegisterOrMemoryRegionIndex];
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byte offsetRegisterIndex = instruction[OffsetRegisterOrImmediateIndex];
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ulong immediate;
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Register addressRegister;
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Register offsetRegister;
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IOperand sourceOperand;
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switch (operandType)
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{
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case MemoryRegionWithOffsetImmediate:
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// *(?x + #a)
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immediate = InstructionHelper.GetImmediate(instruction, OffsetRegisterOrImmediateIndex, OffsetImmediateSize);
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sourceOperand = MemoryHelper.EmitPointer((MemoryRegion)registerOrMemoryRegion, immediate, context);
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break;
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case MemoryRegionWithOffsetRegister:
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// *(?x + $r)
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offsetRegister = context.GetRegister(offsetRegisterIndex);
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sourceOperand = MemoryHelper.EmitPointer((MemoryRegion)registerOrMemoryRegion, offsetRegister, context);
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break;
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case AddressRegisterWithOffsetImmediate:
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// *($R + #a)
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addressRegister = context.GetRegister(registerOrMemoryRegion);
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immediate = InstructionHelper.GetImmediate(instruction, OffsetRegisterOrImmediateIndex, OffsetImmediateSize);
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sourceOperand = MemoryHelper.EmitPointer(addressRegister, immediate, context);
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break;
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case AddressRegisterWithOffsetRegister:
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// *($R + $r)
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addressRegister = context.GetRegister(registerOrMemoryRegion);
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offsetRegister = context.GetRegister(offsetRegisterIndex);
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sourceOperand = MemoryHelper.EmitPointer(addressRegister, offsetRegister, context);
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break;
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case ValueRegister:
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// $V
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sourceOperand = context.GetRegister(registerOrMemoryRegion);
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break;
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default:
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throw new TamperCompilationException($"Invalid operand type {operandType} in Atmosphere cheat");
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}
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InstructionHelper.Emit(typeof(OpLog<>), operationWidth, context, logId, sourceOperand);
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}
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}
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}
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50
Ryujinx.HLE/HOS/Tamper/CodeEmitters/EndConditionalBlock.cs
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50
Ryujinx.HLE/HOS/Tamper/CodeEmitters/EndConditionalBlock.cs
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using Ryujinx.HLE.Exceptions;
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using Ryujinx.HLE.HOS.Tamper.Conditions;
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using Ryujinx.HLE.HOS.Tamper.Operations;
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using System.Collections.Generic;
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namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
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{
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/// <summary>
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/// Code type 2 marks the end of a conditional block (started by Code Type 1, Code Type 8 or Code Type C0).
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/// </summary>
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class EndConditionalBlock
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{
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public static void Emit(byte[] instruction, CompilationContext context)
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{
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// 20000000
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// Use the conditional begin instruction stored in the stack.
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instruction = context.CurrentBlock.BaseInstruction;
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CodeType codeType = InstructionHelper.GetCodeType(instruction);
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// Pop the current block of operations from the stack so control instructions
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// for the conditional can be emitted in the upper block.
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IEnumerable<IOperation> operations = context.CurrentOperations;
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context.BlockStack.Pop();
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ICondition condition;
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switch (codeType)
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{
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case CodeType.BeginMemoryConditionalBlock:
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condition = MemoryConditional.Emit(instruction, context);
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break;
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case CodeType.BeginKeypressConditionalBlock:
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condition = KeyPressConditional.Emit(instruction, context);
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break;
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case CodeType.BeginRegisterConditionalBlock:
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condition = RegisterConditional.Emit(instruction, context);
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break;
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default:
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throw new TamperCompilationException($"Conditional end does not match code type {codeType} in Atmosphere cheat");
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}
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// Create a conditional block with the current operations and nest it in the upper
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// block of the stack.
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IfBlock block = new IfBlock(condition, operations);
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context.CurrentOperations.Add(block);
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}
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}
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}
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26
Ryujinx.HLE/HOS/Tamper/CodeEmitters/KeyPressConditional.cs
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26
Ryujinx.HLE/HOS/Tamper/CodeEmitters/KeyPressConditional.cs
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using Ryujinx.HLE.HOS.Tamper.Conditions;
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namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
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{
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/// <summary>
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/// Code type 8 enters or skips a conditional block based on whether a key combination is pressed.
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/// </summary>
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class KeyPressConditional
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{
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private const int InputMaskIndex = 1;
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private const int InputMaskSize = 7;
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public static ICondition Emit(byte[] instruction, CompilationContext context)
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{
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// 8kkkkkkk
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// k: Keypad mask to check against, see below.
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// Note that for multiple button combinations, the bitmasks should be ORd together.
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// The Keypad Values are the direct output of hidKeysDown().
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ulong inputMask = InstructionHelper.GetImmediate(instruction, InputMaskIndex, InputMaskSize);
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return new InputMask((long)inputMask, context.PressedKeys);
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}
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}
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}
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57
Ryujinx.HLE/HOS/Tamper/CodeEmitters/LegacyArithmetic.cs
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57
Ryujinx.HLE/HOS/Tamper/CodeEmitters/LegacyArithmetic.cs
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using Ryujinx.HLE.Exceptions;
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using Ryujinx.HLE.HOS.Tamper.Operations;
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using System;
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namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
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{
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/// <summary>
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/// Code type 7 allows performing arithmetic on registers. However, it has been deprecated by Code
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/// type 9, and is only kept for backwards compatibility.
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/// </summary>
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class LegacyArithmetic
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{
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const int OperationWidthIndex = 1;
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const int DestinationRegisterIndex = 3;
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const int OperationTypeIndex = 4;
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const int ValueImmediateIndex = 8;
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const int ValueImmediateSize = 8;
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private const byte Add = 0; // reg += rhs
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private const byte Sub = 1; // reg -= rhs
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private const byte Mul = 2; // reg *= rhs
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private const byte Lsh = 3; // reg <<= rhs
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private const byte Rsh = 4; // reg >>= rhs
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public static void Emit(byte[] instruction, CompilationContext context)
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{
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// 7T0RC000 VVVVVVVV
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// T: Width of arithmetic operation(1, 2, 4, or 8 bytes).
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// R: Register to apply arithmetic to.
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// C: Arithmetic operation to apply, see below.
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// V: Value to use for arithmetic operation.
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byte operationWidth = instruction[OperationWidthIndex];
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Register register = context.GetRegister(instruction[DestinationRegisterIndex]);
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byte operation = instruction[OperationTypeIndex];
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ulong immediate = InstructionHelper.GetImmediate(instruction, ValueImmediateIndex, ValueImmediateSize);
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Value<ulong> rightHandSideValue = new Value<ulong>(immediate);
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void Emit(Type operationType)
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{
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InstructionHelper.Emit(operationType, operationWidth, context, register, register, rightHandSideValue);
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}
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switch (operation)
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{
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case Add: Emit(typeof(OpAdd<>)); break;
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case Sub: Emit(typeof(OpSub<>)); break;
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case Mul: Emit(typeof(OpMul<>)); break;
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case Lsh: Emit(typeof(OpLsh<>)); break;
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case Rsh: Emit(typeof(OpRsh<>)); break;
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default:
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throw new TamperCompilationException($"Invalid arithmetic operation {operation} in Atmosphere cheat");
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||||
}
|
||||
}
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||||
}
|
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}
|
|
@ -0,0 +1,28 @@
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using Ryujinx.HLE.HOS.Tamper.Operations;
|
||||
|
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namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
|
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{
|
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/// <summary>
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/// Code type 4 allows setting a register to a constant value.
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/// </summary>
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class LoadRegisterWithConstant
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{
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const int RegisterIndex = 3;
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const int ValueImmediateIndex = 8;
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const int ValueImmediateSize = 16;
|
||||
|
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public static void Emit(byte[] instruction, CompilationContext context)
|
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{
|
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// 400R0000 VVVVVVVV VVVVVVVV
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// R: Register to use.
|
||||
// V: Value to load.
|
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Register destinationRegister = context.GetRegister(instruction[RegisterIndex]);
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ulong immediate = InstructionHelper.GetImmediate(instruction, ValueImmediateIndex, ValueImmediateSize);
|
||||
Value<ulong> sourceValue = new Value<ulong>(immediate);
|
||||
|
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context.CurrentOperations.Add(new OpMov<ulong>(destinationRegister, sourceValue));
|
||||
}
|
||||
}
|
||||
}
|
|
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using Ryujinx.HLE.Exceptions;
|
||||
|
||||
namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
|
||||
{
|
||||
/// <summary>
|
||||
/// Code type 5 allows loading a value from memory into a register, either using a fixed address or by
|
||||
/// dereferencing the destination register.
|
||||
/// </summary>
|
||||
class LoadRegisterWithMemory
|
||||
{
|
||||
private const int OperationWidthIndex = 1;
|
||||
private const int MemoryRegionIndex = 2;
|
||||
private const int DestinationRegisterIndex = 3;
|
||||
private const int UseDestinationAsSourceIndex = 4;
|
||||
private const int OffsetImmediateIndex = 6;
|
||||
|
||||
private const int OffsetImmediateSize = 10;
|
||||
|
||||
public static void Emit(byte[] instruction, CompilationContext context)
|
||||
{
|
||||
// 5TMR00AA AAAAAAAA
|
||||
// T: Width of memory read (1, 2, 4, or 8 bytes).
|
||||
// M: Memory region to write to (0 = Main NSO, 1 = Heap).
|
||||
// R: Register to load value into.
|
||||
// A: Immediate offset to use from memory region base.
|
||||
|
||||
// 5TMR10AA AAAAAAAA
|
||||
// T: Width of memory read(1, 2, 4, or 8 bytes).
|
||||
// M: Ignored.
|
||||
// R: Register to use as base address and to load value into.
|
||||
// A: Immediate offset to use from register R.
|
||||
|
||||
byte operationWidth = instruction[OperationWidthIndex];
|
||||
MemoryRegion memoryRegion = (MemoryRegion)instruction[MemoryRegionIndex];
|
||||
Register destinationRegister = context.GetRegister(instruction[DestinationRegisterIndex]);
|
||||
byte useDestinationAsSourceIndex = instruction[UseDestinationAsSourceIndex];
|
||||
ulong address = InstructionHelper.GetImmediate(instruction, OffsetImmediateIndex, OffsetImmediateSize);
|
||||
|
||||
Pointer sourceMemory;
|
||||
|
||||
switch (useDestinationAsSourceIndex)
|
||||
{
|
||||
case 0:
|
||||
// Don't use the source register as an additional address offset.
|
||||
sourceMemory = MemoryHelper.EmitPointer(memoryRegion, address, context);
|
||||
break;
|
||||
case 1:
|
||||
// Use the source register as the base address.
|
||||
sourceMemory = MemoryHelper.EmitPointer(destinationRegister, address, context);
|
||||
break;
|
||||
default:
|
||||
throw new TamperCompilationException($"Invalid source mode {useDestinationAsSourceIndex} in Atmosphere cheat");
|
||||
}
|
||||
|
||||
InstructionHelper.EmitMov(operationWidth, context, destinationRegister, sourceMemory);
|
||||
}
|
||||
}
|
||||
}
|
45
Ryujinx.HLE/HOS/Tamper/CodeEmitters/MemoryConditional.cs
Normal file
45
Ryujinx.HLE/HOS/Tamper/CodeEmitters/MemoryConditional.cs
Normal file
|
@ -0,0 +1,45 @@
|
|||
using Ryujinx.HLE.HOS.Tamper.Conditions;
|
||||
|
||||
namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
|
||||
{
|
||||
/// <summary>
|
||||
/// Code type 1 performs a comparison of the contents of memory to a static value.
|
||||
/// If the condition is not met, all instructions until the appropriate conditional block terminator
|
||||
/// are skipped.
|
||||
/// </summary>
|
||||
class MemoryConditional
|
||||
{
|
||||
private const int OperationWidthIndex = 1;
|
||||
private const int MemoryRegionIndex = 2;
|
||||
private const int ComparisonTypeIndex = 3;
|
||||
private const int OffsetImmediateIndex = 6;
|
||||
private const int ValueImmediateIndex = 16;
|
||||
|
||||
private const int OffsetImmediateSize = 10;
|
||||
private const int ValueImmediateSize4 = 8;
|
||||
private const int ValueImmediateSize8 = 16;
|
||||
|
||||
public static ICondition Emit(byte[] instruction, CompilationContext context)
|
||||
{
|
||||
// 1TMC00AA AAAAAAAA VVVVVVVV (VVVVVVVV)
|
||||
// T: Width of memory write (1, 2, 4, or 8 bytes).
|
||||
// M: Memory region to write to (0 = Main NSO, 1 = Heap).
|
||||
// C: Condition to use, see below.
|
||||
// A: Immediate offset to use from memory region base.
|
||||
// V: Value to compare to.
|
||||
|
||||
byte operationWidth = instruction[OperationWidthIndex];
|
||||
MemoryRegion memoryRegion = (MemoryRegion)instruction[MemoryRegionIndex];
|
||||
Comparison comparison = (Comparison)instruction[ComparisonTypeIndex];
|
||||
|
||||
ulong address = InstructionHelper.GetImmediate(instruction, OffsetImmediateIndex, OffsetImmediateSize);
|
||||
Pointer sourceMemory = MemoryHelper.EmitPointer(memoryRegion, address, context);
|
||||
|
||||
int valueSize = operationWidth <= 4 ? ValueImmediateSize4 : ValueImmediateSize8;
|
||||
ulong value = InstructionHelper.GetImmediate(instruction, ValueImmediateIndex, valueSize);
|
||||
Value<ulong> compareToValue = new Value<ulong>(value);
|
||||
|
||||
return InstructionHelper.CreateCondition(comparison, operationWidth, sourceMemory, compareToValue);
|
||||
}
|
||||
}
|
||||
}
|
17
Ryujinx.HLE/HOS/Tamper/CodeEmitters/PauseProcess.cs
Normal file
17
Ryujinx.HLE/HOS/Tamper/CodeEmitters/PauseProcess.cs
Normal file
|
@ -0,0 +1,17 @@
|
|||
using Ryujinx.HLE.HOS.Tamper.Operations;
|
||||
|
||||
namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
|
||||
{
|
||||
/// <summary>
|
||||
/// Code type 0xFF0 pauses the current process.
|
||||
/// </summary>
|
||||
class PauseProcess
|
||||
{
|
||||
// FF0?????
|
||||
|
||||
public static void Emit(byte[] instruction, CompilationContext context)
|
||||
{
|
||||
context.CurrentOperations.Add(new OpProcCtrl(context.Process, true));
|
||||
}
|
||||
}
|
||||
}
|
|
@ -0,0 +1,47 @@
|
|||
using Ryujinx.HLE.HOS.Tamper.Operations;
|
||||
|
||||
namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
|
||||
{
|
||||
/// <summary>
|
||||
/// Code type 0xC3 reads or writes a static register with a given register.
|
||||
/// NOTE: Registers are saved and restored to a different set of registers than the ones used
|
||||
/// for the other opcodes (Static Registers).
|
||||
/// </summary>
|
||||
class ReadOrWriteStaticRegister
|
||||
{
|
||||
private const int StaticRegisterIndex = 5;
|
||||
private const int RegisterIndex = 7;
|
||||
|
||||
private const byte FirstWriteRegister = 0x80;
|
||||
|
||||
private const int StaticRegisterSize = 2;
|
||||
|
||||
public static void Emit(byte[] instruction, CompilationContext context)
|
||||
{
|
||||
// C3000XXx
|
||||
// XX: Static register index, 0x00 to 0x7F for reading or 0x80 to 0xFF for writing.
|
||||
// x: Register index.
|
||||
|
||||
ulong staticRegisterIndex = InstructionHelper.GetImmediate(instruction, StaticRegisterIndex, StaticRegisterSize);
|
||||
Register register = context.GetRegister(instruction[RegisterIndex]);
|
||||
|
||||
IOperand sourceRegister;
|
||||
IOperand destinationRegister;
|
||||
|
||||
if (staticRegisterIndex < FirstWriteRegister)
|
||||
{
|
||||
// Read from static register.
|
||||
sourceRegister = context.GetStaticRegister((byte)staticRegisterIndex);
|
||||
destinationRegister = register;
|
||||
}
|
||||
else
|
||||
{
|
||||
// Write to static register.
|
||||
sourceRegister = register;
|
||||
destinationRegister = context.GetStaticRegister((byte)(staticRegisterIndex - FirstWriteRegister));
|
||||
}
|
||||
|
||||
context.CurrentOperations.Add(new OpMov<ulong>(destinationRegister, sourceRegister));
|
||||
}
|
||||
}
|
||||
}
|
106
Ryujinx.HLE/HOS/Tamper/CodeEmitters/RegisterConditional.cs
Normal file
106
Ryujinx.HLE/HOS/Tamper/CodeEmitters/RegisterConditional.cs
Normal file
|
@ -0,0 +1,106 @@
|
|||
using Ryujinx.HLE.Exceptions;
|
||||
using Ryujinx.HLE.HOS.Tamper.Conditions;
|
||||
using Ryujinx.HLE.HOS.Tamper.Operations;
|
||||
|
||||
namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
|
||||
{
|
||||
/// <summary>
|
||||
/// Code type 0xC0 performs a comparison of the contents of a register and another value.
|
||||
/// This code support multiple operand types, see below. If the condition is not met,
|
||||
/// all instructions until the appropriate conditional block terminator are skipped.
|
||||
/// </summary>
|
||||
class RegisterConditional
|
||||
{
|
||||
private const int OperationWidthIndex = 2;
|
||||
private const int ComparisonTypeIndex = 3;
|
||||
private const int SourceRegisterIndex = 4;
|
||||
private const int OperandTypeIndex = 5;
|
||||
private const int RegisterOrMemoryRegionIndex = 6;
|
||||
private const int OffsetImmediateIndex = 7;
|
||||
private const int ValueImmediateIndex = 8;
|
||||
|
||||
private const int MemoryRegionWithOffsetImmediate = 0;
|
||||
private const int MemoryRegionWithOffsetRegister = 1;
|
||||
private const int AddressRegisterWithOffsetImmediate = 2;
|
||||
private const int AddressRegisterWithOffsetRegister = 3;
|
||||
private const int OffsetImmediate = 4;
|
||||
private const int AddressRegister = 5;
|
||||
|
||||
private const int OffsetImmediateSize = 9;
|
||||
private const int ValueImmediateSize8 = 8;
|
||||
private const int ValueImmediateSize16 = 16;
|
||||
|
||||
public static ICondition Emit(byte[] instruction, CompilationContext context)
|
||||
{
|
||||
// C0TcSX##
|
||||
// C0TcS0Ma aaaaaaaa
|
||||
// C0TcS1Mr
|
||||
// C0TcS2Ra aaaaaaaa
|
||||
// C0TcS3Rr
|
||||
// C0TcS400 VVVVVVVV (VVVVVVVV)
|
||||
// C0TcS5X0
|
||||
// T: Width of memory write(1, 2, 4, or 8 bytes).
|
||||
// c: Condition to use, see below.
|
||||
// S: Source Register.
|
||||
// X: Operand Type, see below.
|
||||
// M: Memory Type(operand types 0 and 1).
|
||||
// R: Address Register(operand types 2 and 3).
|
||||
// a: Relative Address(operand types 0 and 2).
|
||||
// r: Offset Register(operand types 1 and 3).
|
||||
// X: Other Register(operand type 5).
|
||||
// V: Value to compare to(operand type 4).
|
||||
|
||||
byte operationWidth = instruction[OperationWidthIndex];
|
||||
Comparison comparison = (Comparison)instruction[ComparisonTypeIndex];
|
||||
Register sourceRegister = context.GetRegister(instruction[SourceRegisterIndex]);
|
||||
byte operandType = instruction[OperandTypeIndex];
|
||||
byte registerOrMemoryRegion = instruction[RegisterOrMemoryRegionIndex];
|
||||
byte offsetRegisterIndex = instruction[OffsetImmediateIndex];
|
||||
ulong offsetImmediate;
|
||||
ulong valueImmediate;
|
||||
int valueImmediateSize;
|
||||
Register addressRegister;
|
||||
Register offsetRegister;
|
||||
IOperand sourceOperand;
|
||||
|
||||
switch (operandType)
|
||||
{
|
||||
case MemoryRegionWithOffsetImmediate:
|
||||
// *(?x + #a)
|
||||
offsetImmediate = InstructionHelper.GetImmediate(instruction, OffsetImmediateIndex, OffsetImmediateSize);
|
||||
sourceOperand = MemoryHelper.EmitPointer((MemoryRegion)registerOrMemoryRegion, offsetImmediate, context);
|
||||
break;
|
||||
case MemoryRegionWithOffsetRegister:
|
||||
// *(?x + $r)
|
||||
offsetRegister = context.GetRegister(offsetRegisterIndex);
|
||||
sourceOperand = MemoryHelper.EmitPointer((MemoryRegion)registerOrMemoryRegion, offsetRegister, context);
|
||||
break;
|
||||
case AddressRegisterWithOffsetImmediate:
|
||||
// *($R + #a)
|
||||
addressRegister = context.GetRegister(registerOrMemoryRegion);
|
||||
offsetImmediate = InstructionHelper.GetImmediate(instruction, OffsetImmediateIndex, OffsetImmediateSize);
|
||||
sourceOperand = MemoryHelper.EmitPointer(addressRegister, offsetImmediate, context);
|
||||
break;
|
||||
case AddressRegisterWithOffsetRegister:
|
||||
// *($R + $r)
|
||||
addressRegister = context.GetRegister(registerOrMemoryRegion);
|
||||
offsetRegister = context.GetRegister(offsetRegisterIndex);
|
||||
sourceOperand = MemoryHelper.EmitPointer(addressRegister, offsetRegister, context);
|
||||
break;
|
||||
case OffsetImmediate:
|
||||
valueImmediateSize = operationWidth <= 4 ? ValueImmediateSize8 : ValueImmediateSize16;
|
||||
valueImmediate = InstructionHelper.GetImmediate(instruction, ValueImmediateIndex, valueImmediateSize);
|
||||
sourceOperand = new Value<ulong>(valueImmediate);
|
||||
break;
|
||||
case AddressRegister:
|
||||
// $V
|
||||
sourceOperand = context.GetRegister(registerOrMemoryRegion);
|
||||
break;
|
||||
default:
|
||||
throw new TamperCompilationException($"Invalid operand type {operandType} in Atmosphere cheat");
|
||||
}
|
||||
|
||||
return InstructionHelper.CreateCondition(comparison, operationWidth, sourceRegister, sourceOperand);
|
||||
}
|
||||
}
|
||||
}
|
17
Ryujinx.HLE/HOS/Tamper/CodeEmitters/ResumeProcess.cs
Normal file
17
Ryujinx.HLE/HOS/Tamper/CodeEmitters/ResumeProcess.cs
Normal file
|
@ -0,0 +1,17 @@
|
|||
using Ryujinx.HLE.HOS.Tamper.Operations;
|
||||
|
||||
namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
|
||||
{
|
||||
/// <summary>
|
||||
/// Code type 0xFF1 resumes the current process.
|
||||
/// </summary>
|
||||
class ResumeProcess
|
||||
{
|
||||
// FF1?????
|
||||
|
||||
public static void Emit(byte[] instruction, CompilationContext context)
|
||||
{
|
||||
context.CurrentOperations.Add(new OpProcCtrl(context.Process, false));
|
||||
}
|
||||
}
|
||||
}
|
65
Ryujinx.HLE/HOS/Tamper/CodeEmitters/SaveOrRestoreRegister.cs
Normal file
65
Ryujinx.HLE/HOS/Tamper/CodeEmitters/SaveOrRestoreRegister.cs
Normal file
|
@ -0,0 +1,65 @@
|
|||
using Ryujinx.HLE.Exceptions;
|
||||
using Ryujinx.HLE.HOS.Tamper.Operations;
|
||||
|
||||
namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
|
||||
{
|
||||
/// <summary>
|
||||
/// Code type 0xC1 performs saving or restoring of registers.
|
||||
/// NOTE: Registers are saved and restored to a different set of registers than the ones used
|
||||
/// for the other opcodes (Save Registers).
|
||||
/// </summary>
|
||||
class SaveOrRestoreRegister
|
||||
{
|
||||
private const int DestinationRegisterIndex = 3;
|
||||
private const int SourceRegisterIndex = 5;
|
||||
private const int OperationTypeIndex = 6;
|
||||
|
||||
private const int RestoreRegister = 0;
|
||||
private const int SaveRegister = 1;
|
||||
private const int ClearSavedValue = 2;
|
||||
private const int ClearRegister = 3;
|
||||
|
||||
public static void Emit(byte[] instruction, CompilationContext context)
|
||||
{
|
||||
// C10D0Sx0
|
||||
// D: Destination index.
|
||||
// S: Source index.
|
||||
// x: Operand Type, see below.
|
||||
|
||||
byte destinationRegIndex = instruction[DestinationRegisterIndex];
|
||||
byte sourceRegIndex = instruction[SourceRegisterIndex];
|
||||
byte operationType = instruction[OperationTypeIndex];
|
||||
Impl(operationType, destinationRegIndex, sourceRegIndex, context);
|
||||
}
|
||||
|
||||
public static void Impl(byte operationType, byte destinationRegIndex, byte sourceRegIndex, CompilationContext context)
|
||||
{
|
||||
IOperand destinationOperand;
|
||||
IOperand sourceOperand;
|
||||
|
||||
switch (operationType)
|
||||
{
|
||||
case RestoreRegister:
|
||||
destinationOperand = context.GetRegister(destinationRegIndex);
|
||||
sourceOperand = context.GetSavedRegister(sourceRegIndex);
|
||||
break;
|
||||
case SaveRegister:
|
||||
destinationOperand = context.GetSavedRegister(destinationRegIndex);
|
||||
sourceOperand = context.GetRegister(sourceRegIndex);
|
||||
break;
|
||||
case ClearSavedValue:
|
||||
destinationOperand = new Value<ulong>(0);
|
||||
sourceOperand = context.GetSavedRegister(sourceRegIndex);
|
||||
break;
|
||||
case ClearRegister:
|
||||
destinationOperand = new Value<ulong>(0);
|
||||
sourceOperand = context.GetRegister(sourceRegIndex);
|
||||
break;
|
||||
default:
|
||||
throw new TamperCompilationException($"Invalid register operation type {operationType} in Atmosphere cheat");
|
||||
}
|
||||
|
||||
context.CurrentOperations.Add(new OpMov<ulong>(destinationOperand, sourceOperand));
|
||||
}
|
||||
}
|
||||
}
|
|
@ -0,0 +1,33 @@
|
|||
namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
|
||||
{
|
||||
/// <summary>
|
||||
/// Code type 0xC2 performs saving or restoring of multiple registers using a bitmask.
|
||||
/// NOTE: Registers are saved and restored to a different set of registers than the ones used
|
||||
/// for the other opcodes (Save Registers).
|
||||
/// </summary>
|
||||
class SaveOrRestoreRegisterWithMask
|
||||
{
|
||||
private const int OperationTypeIndex = 2;
|
||||
private const int RegisterMaskIndex = 4;
|
||||
|
||||
private const int RegisterMaskSize = 4;
|
||||
|
||||
public static void Emit(byte[] instruction, CompilationContext context)
|
||||
{
|
||||
// C2x0XXXX
|
||||
// x: Operand Type, see below.
|
||||
// X: 16-bit bitmask, bit i == save or restore register i.
|
||||
|
||||
byte operationType = instruction[OperationTypeIndex];
|
||||
ulong mask = InstructionHelper.GetImmediate(instruction, RegisterMaskIndex, RegisterMaskSize);
|
||||
|
||||
for (byte regIndex = 0; mask != 0; mask >>= 1, regIndex++)
|
||||
{
|
||||
if ((mask & 0x1) != 0)
|
||||
{
|
||||
SaveOrRestoreRegister.Impl(operationType, regIndex, regIndex, context);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
72
Ryujinx.HLE/HOS/Tamper/CodeEmitters/StartEndLoop.cs
Normal file
72
Ryujinx.HLE/HOS/Tamper/CodeEmitters/StartEndLoop.cs
Normal file
|
@ -0,0 +1,72 @@
|
|||
using Ryujinx.HLE.Exceptions;
|
||||
using Ryujinx.HLE.HOS.Tamper.Operations;
|
||||
|
||||
namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
|
||||
{
|
||||
/// <summary>
|
||||
/// Code type 3 allows for iterating in a loop a fixed number of times.
|
||||
/// </summary>
|
||||
class StartEndLoop
|
||||
{
|
||||
private const int StartOrEndIndex = 1;
|
||||
private const int IterationRegisterIndex = 3;
|
||||
private const int IterationsImmediateIndex = 8;
|
||||
|
||||
private const int IterationsImmediateSize = 8;
|
||||
|
||||
private const byte LoopBegin = 0;
|
||||
private const byte LoopEnd = 1;
|
||||
|
||||
public static void Emit(byte[] instruction, CompilationContext context)
|
||||
{
|
||||
// 300R0000 VVVVVVVV
|
||||
// R: Register to use as loop counter.
|
||||
// V: Number of iterations to loop.
|
||||
|
||||
// 310R0000
|
||||
|
||||
byte mode = instruction[StartOrEndIndex];
|
||||
byte iterationRegisterIndex = instruction[IterationRegisterIndex];
|
||||
|
||||
switch (mode)
|
||||
{
|
||||
case LoopBegin:
|
||||
// Just start a new compilation block and parse the instruction itself at the end.
|
||||
context.BlockStack.Push(new OperationBlock(instruction));
|
||||
return;
|
||||
case LoopEnd:
|
||||
break;
|
||||
default:
|
||||
throw new TamperCompilationException($"Invalid loop {mode} in Atmosphere cheat");
|
||||
}
|
||||
|
||||
// Use the loop begin instruction stored in the stack.
|
||||
instruction = context.CurrentBlock.BaseInstruction;
|
||||
CodeType codeType = InstructionHelper.GetCodeType(instruction);
|
||||
|
||||
if (codeType != CodeType.StartEndLoop)
|
||||
{
|
||||
throw new TamperCompilationException($"Loop end does not match code type {codeType} in Atmosphere cheat");
|
||||
}
|
||||
|
||||
// Validate if the register in the beginning and end are the same.
|
||||
|
||||
byte oldIterationRegisterIndex = instruction[IterationRegisterIndex];
|
||||
|
||||
if (iterationRegisterIndex != oldIterationRegisterIndex)
|
||||
{
|
||||
throw new TamperCompilationException($"The register used for the loop changed from {oldIterationRegisterIndex} to {iterationRegisterIndex} in Atmosphere cheat");
|
||||
}
|
||||
|
||||
Register iterationRegister = context.GetRegister(iterationRegisterIndex);
|
||||
ulong immediate = InstructionHelper.GetImmediate(instruction, IterationsImmediateIndex, IterationsImmediateSize);
|
||||
|
||||
// Create a loop block with the current operations and nest it in the upper
|
||||
// block of the stack.
|
||||
|
||||
ForBlock block = new ForBlock(immediate, iterationRegister, context.CurrentOperations);
|
||||
context.BlockStack.Pop();
|
||||
context.CurrentOperations.Add(block);
|
||||
}
|
||||
}
|
||||
}
|
|
@ -0,0 +1,41 @@
|
|||
namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
|
||||
{
|
||||
/// <summary>
|
||||
/// Code type 0 allows writing a static value to a memory address.
|
||||
/// </summary>
|
||||
class StoreConstantToAddress
|
||||
{
|
||||
private const int OperationWidthIndex = 1;
|
||||
private const int MemoryRegionIndex = 2;
|
||||
private const int OffsetRegisterIndex = 3;
|
||||
private const int OffsetImmediateIndex = 6;
|
||||
private const int ValueImmediateIndex = 16;
|
||||
|
||||
private const int OffsetImmediateSize = 10;
|
||||
private const int ValueImmediateSize8 = 8;
|
||||
private const int ValueImmediateSize16 = 16;
|
||||
|
||||
public static void Emit(byte[] instruction, CompilationContext context)
|
||||
{
|
||||
// 0TMR00AA AAAAAAAA VVVVVVVV (VVVVVVVV)
|
||||
// T: Width of memory write(1, 2, 4, or 8 bytes).
|
||||
// M: Memory region to write to(0 = Main NSO, 1 = Heap).
|
||||
// R: Register to use as an offset from memory region base.
|
||||
// A: Immediate offset to use from memory region base.
|
||||
// V: Value to write.
|
||||
|
||||
byte operationWidth = instruction[OperationWidthIndex];
|
||||
MemoryRegion memoryRegion = (MemoryRegion)instruction[MemoryRegionIndex];
|
||||
Register offsetRegister = context.GetRegister(instruction[OffsetRegisterIndex]);
|
||||
ulong offsetImmediate = InstructionHelper.GetImmediate(instruction, OffsetImmediateIndex, OffsetImmediateSize);
|
||||
|
||||
Pointer dstMem = MemoryHelper.EmitPointer(memoryRegion, offsetRegister, offsetImmediate, context);
|
||||
|
||||
int valueImmediateSize = operationWidth <= 4 ? ValueImmediateSize8 : ValueImmediateSize16;
|
||||
ulong valueImmediate = InstructionHelper.GetImmediate(instruction, ValueImmediateIndex, valueImmediateSize);
|
||||
Value<ulong> storeValue = new Value<ulong>(valueImmediate);
|
||||
|
||||
InstructionHelper.EmitMov(operationWidth, context, dstMem, storeValue);
|
||||
}
|
||||
}
|
||||
}
|
71
Ryujinx.HLE/HOS/Tamper/CodeEmitters/StoreConstantToMemory.cs
Normal file
71
Ryujinx.HLE/HOS/Tamper/CodeEmitters/StoreConstantToMemory.cs
Normal file
|
@ -0,0 +1,71 @@
|
|||
using Ryujinx.HLE.Exceptions;
|
||||
using Ryujinx.HLE.HOS.Tamper.Operations;
|
||||
|
||||
namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
|
||||
{
|
||||
/// <summary>
|
||||
/// Code type 6 allows writing a fixed value to a memory address specified by a register.
|
||||
/// </summary>
|
||||
class StoreConstantToMemory
|
||||
{
|
||||
private const int OperationWidthIndex = 1;
|
||||
private const int AddressRegisterIndex = 3;
|
||||
private const int IncrementAddressRegisterIndex = 4;
|
||||
private const int UseOffsetRegisterIndex = 5;
|
||||
private const int OffsetRegisterIndex = 6;
|
||||
private const int ValueImmediateIndex = 8;
|
||||
|
||||
private const int ValueImmediateSize = 16;
|
||||
|
||||
public static void Emit(byte[] instruction, CompilationContext context)
|
||||
{
|
||||
// 6T0RIor0 VVVVVVVV VVVVVVVV
|
||||
// T: Width of memory write(1, 2, 4, or 8 bytes).
|
||||
// R: Register used as base memory address.
|
||||
// I: Increment register flag(0 = do not increment R, 1 = increment R by T).
|
||||
// o: Offset register enable flag(0 = do not add r to address, 1 = add r to address).
|
||||
// r: Register used as offset when o is 1.
|
||||
// V: Value to write to memory.
|
||||
|
||||
byte operationWidth = instruction[OperationWidthIndex];
|
||||
Register sourceRegister = context.GetRegister(instruction[AddressRegisterIndex]);
|
||||
byte incrementAddressRegister = instruction[IncrementAddressRegisterIndex];
|
||||
byte useOffsetRegister = instruction[UseOffsetRegisterIndex];
|
||||
ulong immediate = InstructionHelper.GetImmediate(instruction, ValueImmediateIndex, ValueImmediateSize);
|
||||
Value<ulong> storeValue = new Value<ulong>(immediate);
|
||||
|
||||
Pointer destinationMemory;
|
||||
|
||||
switch (useOffsetRegister)
|
||||
{
|
||||
case 0:
|
||||
// Don't offset the address register by another register.
|
||||
destinationMemory = MemoryHelper.EmitPointer(sourceRegister, context);
|
||||
break;
|
||||
case 1:
|
||||
// Replace the source address by the sum of the base and offset registers.
|
||||
Register offsetRegister = context.GetRegister(instruction[OffsetRegisterIndex]);
|
||||
destinationMemory = MemoryHelper.EmitPointer(sourceRegister, offsetRegister, context);
|
||||
break;
|
||||
default:
|
||||
throw new TamperCompilationException($"Invalid offset mode {useOffsetRegister} in Atmosphere cheat");
|
||||
}
|
||||
|
||||
InstructionHelper.EmitMov(operationWidth, context, destinationMemory, storeValue);
|
||||
|
||||
switch (incrementAddressRegister)
|
||||
{
|
||||
case 0:
|
||||
// Don't increment the address register by operationWidth.
|
||||
break;
|
||||
case 1:
|
||||
// Increment the address register by operationWidth.
|
||||
IOperand increment = new Value<ulong>(operationWidth);
|
||||
context.CurrentOperations.Add(new OpAdd<ulong>(sourceRegister, sourceRegister, increment));
|
||||
break;
|
||||
default:
|
||||
throw new TamperCompilationException($"Invalid increment mode {incrementAddressRegister} in Atmosphere cheat");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
99
Ryujinx.HLE/HOS/Tamper/CodeEmitters/StoreRegisterToMemory.cs
Normal file
99
Ryujinx.HLE/HOS/Tamper/CodeEmitters/StoreRegisterToMemory.cs
Normal file
|
@ -0,0 +1,99 @@
|
|||
using Ryujinx.HLE.Exceptions;
|
||||
using Ryujinx.HLE.HOS.Tamper.Operations;
|
||||
|
||||
namespace Ryujinx.HLE.HOS.Tamper.CodeEmitters
|
||||
{
|
||||
/// <summary>
|
||||
/// Code type 10 allows writing a register to memory.
|
||||
/// </summary>
|
||||
class StoreRegisterToMemory
|
||||
{
|
||||
private const int OperationWidthIndex = 1;
|
||||
private const int SourceRegisterIndex = 2;
|
||||
private const int AddressRegisterIndex = 3;
|
||||
private const int IncrementAddressRegisterIndex = 4;
|
||||
private const int AddressingTypeIndex = 5;
|
||||
private const int RegisterOrMemoryRegionIndex = 6;
|
||||
private const int OffsetImmediateIndex = 7;
|
||||
|
||||
private const int AddressRegister = 0;
|
||||
private const int AddressRegisterWithOffsetRegister = 1;
|
||||
private const int OffsetImmediate = 2;
|
||||
private const int MemoryRegionWithOffsetRegister = 3;
|
||||
private const int MemoryRegionWithOffsetImmediate = 4;
|
||||
private const int MemoryRegionWithOffsetRegisterAndImmediate = 5;
|
||||
|
||||
private const int OffsetImmediateSize1 = 1;
|
||||
private const int OffsetImmediateSize9 = 9;
|
||||
|
||||
public static void Emit(byte[] instruction, CompilationContext context)
|
||||
{
|
||||
// ATSRIOxa (aaaaaaaa)
|
||||
// T: Width of memory write (1, 2, 4, or 8 bytes).
|
||||
// S: Register to write to memory.
|
||||
// R: Register to use as base address.
|
||||
// I: Increment register flag (0 = do not increment R, 1 = increment R by T).
|
||||
// O: Offset type, see below.
|
||||
// x: Register used as offset when O is 1, Memory type when O is 3, 4 or 5.
|
||||
// a: Value used as offset when O is 2, 4 or 5.
|
||||
|
||||
byte operationWidth = instruction[OperationWidthIndex];
|
||||
Register sourceRegister = context.GetRegister(instruction[SourceRegisterIndex]);
|
||||
Register addressRegister = context.GetRegister(instruction[AddressRegisterIndex]);
|
||||
byte incrementAddressRegister = instruction[IncrementAddressRegisterIndex];
|
||||
byte offsetType = instruction[AddressingTypeIndex];
|
||||
byte registerOrMemoryRegion = instruction[RegisterOrMemoryRegionIndex];
|
||||
int immediateSize = instruction.Length <= 8 ? OffsetImmediateSize1 : OffsetImmediateSize9;
|
||||
ulong immediate = InstructionHelper.GetImmediate(instruction, OffsetImmediateIndex, immediateSize);
|
||||
|
||||
Pointer destinationMemory;
|
||||
|
||||
switch (offsetType)
|
||||
{
|
||||
case AddressRegister:
|
||||
// *($R) = $S
|
||||
destinationMemory = MemoryHelper.EmitPointer(addressRegister, context);
|
||||
break;
|
||||
case AddressRegisterWithOffsetRegister:
|
||||
// *($R + $x) = $S
|
||||
Register offsetRegister = context.GetRegister(registerOrMemoryRegion);
|
||||
destinationMemory = MemoryHelper.EmitPointer(addressRegister, offsetRegister, context);
|
||||
break;
|
||||
case OffsetImmediate:
|
||||
// *(#a) = $S
|
||||
destinationMemory = MemoryHelper.EmitPointer(addressRegister, immediate, context);
|
||||
break;
|
||||
case MemoryRegionWithOffsetRegister:
|
||||
// *(?x + $R) = $S
|
||||
destinationMemory = MemoryHelper.EmitPointer((MemoryRegion)registerOrMemoryRegion, addressRegister, context);
|
||||
break;
|
||||
case MemoryRegionWithOffsetImmediate:
|
||||
// *(?x + #a) = $S
|
||||
destinationMemory = MemoryHelper.EmitPointer((MemoryRegion)registerOrMemoryRegion, immediate, context);
|
||||
break;
|
||||
case MemoryRegionWithOffsetRegisterAndImmediate:
|
||||
// *(?x + #a + $R) = $S
|
||||
destinationMemory = MemoryHelper.EmitPointer((MemoryRegion)registerOrMemoryRegion, addressRegister, immediate, context);
|
||||
break;
|
||||
default:
|
||||
throw new TamperCompilationException($"Invalid offset type {offsetType} in Atmosphere cheat");
|
||||
}
|
||||
|
||||
InstructionHelper.EmitMov(operationWidth, context, destinationMemory, sourceRegister);
|
||||
|
||||
switch (incrementAddressRegister)
|
||||
{
|
||||
case 0:
|
||||
// Don't increment the address register by operationWidth.
|
||||
break;
|
||||
case 1:
|
||||
// Increment the address register by operationWidth.
|
||||
IOperand increment = new Value<ulong>(operationWidth);
|
||||
context.CurrentOperations.Add(new OpAdd<ulong>(addressRegister, addressRegister, increment));
|
||||
break;
|
||||
default:
|
||||
throw new TamperCompilationException($"Invalid increment mode {incrementAddressRegister} in Atmosphere cheat");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
Loading…
Add table
Add a link
Reference in a new issue