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Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)

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* Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics, some CQ improvements

* Remove useless space

* Address PR feedback

* Revert EmitVectorZero32_128 changes
This commit is contained in:
gdkchan 2018-09-26 23:30:21 -03:00 • committed by GitHub
parent 40282da93a
commit 0b52ee6627
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GPG key ID: 4AEE18F83AFDEB23
8 changed files with 896 additions and 276 deletions
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8
ChocolArm64/Memory/AMemory.cs
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@ -232,7 +232,7 @@ namespace ChocolArm64.Memory
}
}
[MethodImpl(MethodImplOptions.NoInlining)]
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public Vector128<float> ReadVector32(long Position)
{
if (Sse.IsSupported)
@ -245,7 +245,7 @@ namespace ChocolArm64.Memory
}
}
[MethodImpl(MethodImplOptions.NoInlining)]
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public Vector128<float> ReadVector64(long Position)
{
if (Sse2.IsSupported)
@ -365,7 +365,7 @@ namespace ChocolArm64.Memory
}
}
[MethodImpl(MethodImplOptions.NoInlining)]
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public void WriteVector32(long Position, Vector128<float> Value)
{
if (Sse.IsSupported)
@ -378,7 +378,7 @@ namespace ChocolArm64.Memory
}
}
[MethodImpl(MethodImplOptions.NoInlining)]
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public void WriteVector64(long Position, Vector128<float> Value)
{
if (Sse2.IsSupported)