Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
* Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics, some CQ improvements * Remove useless space * Address PR feedback * Revert EmitVectorZero32_128 changes
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gdkchan
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8 changed files with 896 additions and 276 deletions
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@ -4,7 +4,6 @@ using ChocolArm64.Translation;
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using System;
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using System.Reflection;
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using System.Reflection.Emit;
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using System.Runtime.CompilerServices;
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using System.Runtime.Intrinsics;
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using System.Runtime.Intrinsics.X86;
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@ -12,6 +11,38 @@ namespace ChocolArm64.Instruction
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{
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static class AInstEmitSimdHelper
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{
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public static readonly Type[] IntTypesPerSizeLog2 = new Type[]
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{
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typeof(sbyte),
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typeof(short),
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typeof(int),
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typeof(long)
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};
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public static readonly Type[] UIntTypesPerSizeLog2 = new Type[]
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{
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typeof(byte),
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typeof(ushort),
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typeof(uint),
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typeof(ulong)
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};
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public static readonly Type[] VectorIntTypesPerSizeLog2 = new Type[]
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{
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typeof(Vector128<sbyte>),
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typeof(Vector128<short>),
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typeof(Vector128<int>),
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typeof(Vector128<long>)
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};
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public static readonly Type[] VectorUIntTypesPerSizeLog2 = new Type[]
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{
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typeof(Vector128<byte>),
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typeof(Vector128<ushort>),
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typeof(Vector128<uint>),
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typeof(Vector128<ulong>)
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};
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[Flags]
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public enum OperFlags
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{
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@ -36,56 +67,32 @@ namespace ChocolArm64.Instruction
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return (8 << (Op.Size + 1)) - Op.Imm;
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public static void EmitSse2Call(AILEmitterCtx Context, string Name)
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public static void EmitSse2Op(AILEmitterCtx Context, string Name)
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{
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EmitSseCall(Context, Name, typeof(Sse2));
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EmitSseOp(Context, Name, typeof(Sse2));
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public static void EmitSse41Call(AILEmitterCtx Context, string Name)
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public static void EmitSse41Op(AILEmitterCtx Context, string Name)
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{
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EmitSseCall(Context, Name, typeof(Sse41));
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EmitSseOp(Context, Name, typeof(Sse41));
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public static void EmitSse42Call(AILEmitterCtx Context, string Name)
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public static void EmitSse42Op(AILEmitterCtx Context, string Name)
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{
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EmitSseCall(Context, Name, typeof(Sse42));
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EmitSseOp(Context, Name, typeof(Sse42));
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}
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private static void EmitSseCall(AILEmitterCtx Context, string Name, Type Type)
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private static void EmitSseOp(AILEmitterCtx Context, string Name, Type Type)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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void Ldvec(int Reg)
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{
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Context.EmitLdvec(Reg);
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EmitLdvecWithSignedCast(Context, Op.Rn, Op.Size);
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switch (Op.Size)
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{
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case 0: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToSByte)); break;
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case 1: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToInt16)); break;
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case 2: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToInt32)); break;
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case 3: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToInt64)); break;
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}
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}
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Ldvec(Op.Rn);
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Type BaseType = null;
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switch (Op.Size)
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{
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case 0: BaseType = typeof(Vector128<sbyte>); break;
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case 1: BaseType = typeof(Vector128<short>); break;
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case 2: BaseType = typeof(Vector128<int>); break;
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case 3: BaseType = typeof(Vector128<long>); break;
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}
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Type BaseType = VectorIntTypesPerSizeLog2[Op.Size];
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if (Op is AOpCodeSimdReg BinOp)
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{
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Ldvec(BinOp.Rm);
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EmitLdvecWithSignedCast(Context, BinOp.Rm, Op.Size);
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Context.EmitCall(Type.GetMethod(Name, new Type[] { BaseType, BaseType }));
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}
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@ -94,15 +101,7 @@ namespace ChocolArm64.Instruction
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Context.EmitCall(Type.GetMethod(Name, new Type[] { BaseType }));
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}
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switch (Op.Size)
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{
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case 0: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSByteToSingle)); break;
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case 1: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInt16ToSingle)); break;
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case 2: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInt32ToSingle)); break;
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case 3: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInt64ToSingle)); break;
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}
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Context.EmitStvec(Op.Rd);
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EmitStvecWithSignedCast(Context, Op.Rd, Op.Size);
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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@ -110,17 +109,91 @@ namespace ChocolArm64.Instruction
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}
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}
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public static void EmitScalarSseOrSse2CallF(AILEmitterCtx Context, string Name)
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public static void EmitLdvecWithSignedCast(AILEmitterCtx Context, int Reg, int Size)
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{
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EmitSseOrSse2CallF(Context, Name, true);
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Context.EmitLdvec(Reg);
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switch (Size)
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{
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case 0: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToSByte)); break;
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case 1: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToInt16)); break;
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case 2: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToInt32)); break;
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case 3: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToInt64)); break;
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default: throw new ArgumentOutOfRangeException(nameof(Size));
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}
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}
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public static void EmitVectorSseOrSse2CallF(AILEmitterCtx Context, string Name)
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public static void EmitLdvecWithCastToDouble(AILEmitterCtx Context, int Reg)
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{
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EmitSseOrSse2CallF(Context, Name, false);
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Context.EmitLdvec(Reg);
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AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToDouble));
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}
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public static void EmitSseOrSse2CallF(AILEmitterCtx Context, string Name, bool Scalar)
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public static void EmitStvecWithCastFromDouble(AILEmitterCtx Context, int Reg)
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{
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AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorDoubleToSingle));
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Context.EmitStvec(Reg);
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}
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public static void EmitLdvecWithUnsignedCast(AILEmitterCtx Context, int Reg, int Size)
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{
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Context.EmitLdvec(Reg);
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switch (Size)
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{
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case 0: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToByte)); break;
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case 1: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToUInt16)); break;
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case 2: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToUInt32)); break;
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case 3: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleToUInt64)); break;
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default: throw new ArgumentOutOfRangeException(nameof(Size));
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}
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}
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public static void EmitStvecWithSignedCast(AILEmitterCtx Context, int Reg, int Size)
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{
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switch (Size)
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{
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case 0: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSByteToSingle)); break;
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case 1: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInt16ToSingle)); break;
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case 2: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInt32ToSingle)); break;
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case 3: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorInt64ToSingle)); break;
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default: throw new ArgumentOutOfRangeException(nameof(Size));
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}
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Context.EmitStvec(Reg);
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}
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public static void EmitStvecWithUnsignedCast(AILEmitterCtx Context, int Reg, int Size)
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{
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switch (Size)
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{
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case 0: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorByteToSingle)); break;
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case 1: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorUInt16ToSingle)); break;
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case 2: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorUInt32ToSingle)); break;
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case 3: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorUInt64ToSingle)); break;
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default: throw new ArgumentOutOfRangeException(nameof(Size));
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}
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Context.EmitStvec(Reg);
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}
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public static void EmitScalarSseOrSse2OpF(AILEmitterCtx Context, string Name)
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{
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EmitSseOrSse2OpF(Context, Name, true);
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}
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public static void EmitVectorSseOrSse2OpF(AILEmitterCtx Context, string Name)
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{
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EmitSseOrSse2OpF(Context, Name, false);
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}
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public static void EmitSseOrSse2OpF(AILEmitterCtx Context, string Name, bool Scalar)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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@ -1183,8 +1256,21 @@ namespace ChocolArm64.Instruction
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public static void EmitScalarSetF(AILEmitterCtx Context, int Reg, int Size)
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{
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EmitVectorZeroAll(Context, Reg);
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EmitVectorInsertF(Context, Reg, 0, Size);
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if (AOptimizations.UseSse41 && Size == 0)
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{
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//If the type is float, we can perform insertion and
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//zero the upper bits with a single instruction (INSERTPS);
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Context.EmitLdvec(Reg);
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AVectorHelper.EmitCall(Context, nameof(AVectorHelper.Sse41VectorInsertScalarSingle));
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Context.EmitStvec(Reg);
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}
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else
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{
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EmitVectorZeroAll(Context, Reg);
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EmitVectorInsertF(Context, Reg, 0, Size);
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}
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}
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public static void EmitVectorExtractSx(AILEmitterCtx Context, int Reg, int Index, int Size)
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@ -1235,8 +1321,17 @@ namespace ChocolArm64.Instruction
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public static void EmitVectorZeroAll(AILEmitterCtx Context, int Rd)
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{
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EmitVectorZeroLower(Context, Rd);
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EmitVectorZeroUpper(Context, Rd);
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if (AOptimizations.UseSse2)
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{
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AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSingleZero));
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Context.EmitStvec(Rd);
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}
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else
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{
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EmitVectorZeroLower(Context, Rd);
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EmitVectorZeroUpper(Context, Rd);
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}
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}
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public static void EmitVectorZeroLower(AILEmitterCtx Context, int Rd)
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@ -1249,9 +1344,32 @@ namespace ChocolArm64.Instruction
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EmitVectorInsertTmp(Context, 0, 3, 0);
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}
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public static void EmitVectorZeroUpper(AILEmitterCtx Context, int Rd)
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public static void EmitVectorZeroUpper(AILEmitterCtx Context, int Reg)
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{
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EmitVectorInsert(Context, Rd, 1, 3, 0);
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if (AOptimizations.UseSse2)
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{
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//TODO: Use MoveScalar once it is fixed, as of the
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//time of writing it just crashes the JIT.
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EmitLdvecWithUnsignedCast(Context, Reg, 3);
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Type[] Types = new Type[] { typeof(Vector128<ulong>), typeof(byte) };
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//Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.MoveScalar), Types));
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Context.EmitLdc_I4(8);
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftLeftLogical128BitLane), Types));
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Context.EmitLdc_I4(8);
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Context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.ShiftRightLogical128BitLane), Types));
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EmitStvecWithUnsignedCast(Context, Reg, 3);
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}
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else
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{
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EmitVectorInsert(Context, Reg, 1, 3, 0);
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}
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}
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public static void EmitVectorZero32_128(AILEmitterCtx Context, int Reg)
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